Abstract: Provided is a structure with a conductive plug including a substrate, a first dielectric layer, an etch stop layer, a second dielectric layer, a conductive plug and a liner. The substrate has a conductive region therein. The first dielectric layer, the etch stop layer and the second dielectric layer are sequentially formed on the substrate and have at least one opening therethrough. Besides, the opening has a substantially vertical sidewall. The conductive plug fills in the opening and is electrically connected to the conductive region. The liner surrounds the upper portion of the conductive plug. A method of forming a structure with a conductive plug is further provided.

Abstract: A super junction semiconductor device includes a semiconductor portion including mesa regions protruding from a base section and spatially separated in a lateral direction parallel to a first surface of the semiconductor portion, and a compensation structure covering at least sidewalls of the mesa regions. The compensation structure includes at least two first compensation layers of a first conductivity type, at least two second compensation layers of a complementary second conductivity type, and at least one interdiffusion layer between one of the first and one of the second compensation layers.

Abstract: A variation in electrical characteristics, such as a negative shift of the threshold voltage or an increase in S value, of a fin-type transistor including an oxide semiconductor material is prevented. An oxide semiconductor film is sandwiched between a plurality of gate electrodes with an insulating film provided between the oxide semiconductor film and each of the gate electrodes. Specifically, a first gate insulating film is provided to cover a first gate electrode, an oxide semiconductor film is provided to be in contact with the first gate insulating film and extend beyond the first gate electrode, a second gate insulating film is provided to cover at least the oxide semiconductor film, and a second gate electrode is provided to be in contact with part of the second gate insulating film and extend beyond the first gate electrode.

Abstract: The present disclosure provides an organic light emitting diode array substrate and its manufacturing method, as well as a display device. The organic light emitting diode array substrate includes: gate lines, data lines, and a plurality of pixel units defined by the gate lines and the data lines. Each pixel unit comprises a first region which emits light and a second region which does not emit light. The first region is provided with an organic light emitting diode, and the second region is provided with a conductive unit which is electrically connected in parallel with the data line and created from the same layer from which a cathode of the organic light emitting diode is created.

Abstract: Semiconductor substrates and methods for processing semiconductor substrates are provided. A method for processing a semiconductor substrate includes providing a semiconductor substrate having an outer edge, a central region, and a peripheral region between the outer edge and the central region. The semiconductor substrate also has an upper surface. The method includes forming an amorphous material over the upper surface of the semiconductor substrate in the peripheral region. Also, the method includes irradiating the upper surface of the semiconductor substrate, wherein the amorphous material inhibits cracking at the outer edge of the semiconductor substrate.

Abstract: A photodetector may have a structure including conductive patterns and an intermediate layer interposed between the conductive patterns. A length L of at least one side of the second conductive pattern that overlaps the first conductive pattern and the intermediate layer satisfies the equation L=?/2neff, wherein the neff is an effective refractive index of a surface plasmon waveguide formed of the first conductive pattern, the intermediate layer, and the second conductive pattern during a surface plasmon resonance. Heat generated in the intermediate layer when the electromagnetic wave having the wavelength ? is incident thereon generates a current variation.

Abstract: A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells. The semiconductor device also includes a redistribution layer electrically coupled to the plurality of LDMOS cells and a plurality of metallic pillars distributed over and electrically coupled to the redistribution layer.

Abstract: A semiconductor package that includes a package substrate, a lower semiconductor chip mounted on the package substrate, and an upper semiconductor chip stacked on the lower semiconductor chip in a cascade shape is provided. An active surface of the lower semiconductor chip is facing an active surface of the upper semiconductor chip.

Abstract: A semiconductor integrated circuit includes a substrate, a multi-gate transistor device formed on the substrate, and an n-well resistor formed in the substrate. The substrate includes a plurality of first isolation structures and at least a second isolation structure formed therein. A depth of the first isolation structures is smaller than a depth of the second isolation structure. The multi-gate transistor device includes a plurality of fin structures, and the fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The n-well resistor includes at least one first isolation structure. The n-well resistor and the multi-gate transistor device are electrically isolated from each other by the second isolation structure.

Abstract: A method of manufacturing through silicon via stacked structures. A plurality of substrates is provided. At least one tapered hole is formed on one surface of each substrate. Each tapered hole is filled up with a tapered through silicon via. A recessed portion is formed on the wider end of each tapered through silicon via. A part of the substrate is removed until the narrower end of each tapered through silicon via protrudes from the other surface of the substrate. The substrates is stacked one after another by fitting and jointing the narrower end of each tapered through silicon via on one substrate into a corresponding recessed portion of the tapered through silicon via of another substrate.

Abstract: The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a patterned dielectric layer having a plurality of first openings. The method includes forming a conductive liner layer over the patterned dielectric layer, the conductive liner layer partially filling the first openings. The method includes forming a trench mask layer over portions of the conductive liner layer outside the first openings, thereby forming a plurality of second openings, a subset of which are formed over the first openings. The method includes depositing a conductive material in the first openings to form a plurality of vias and in the second openings to form a plurality of metal lines. The method includes removing the trench mask layer.

Abstract: What is specified is an optoelectronic component comprising a layer sequence having an active layer, which emits primary electromagnetic radiation, and at least one transparent coupling-out element arranged in the beam path of the primary electromagnetic radiation. The at least one transparent coupling-out element comprises a hybrid material or is produced from a hybrid material.

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

Abstract: Micromachined ultrasonic transducers formed in complementary metal oxide semiconductor (CMOS) wafers are described, as are methods of fabricating such devices. A metallization layer of a CMOS wafer may be removed by sacrificial release to create a cavity of an ultrasonic transducer. Remaining layers may form a membrane of the ultrasonic transducer.

Abstract: A semiconductor device having an electric fuse structure which receives an electric current to permit the electric fuse to be cut without damaging portions around the fuse. The electric fuse can be electrically connected between an electronic circuit and a redundant circuit as a spare of the electronic circuit. After these circuits are sealed with a resin, the fuse can be cut by receiving the electric current from the outside. The electric fuse is formed in a fine layer, and is made of a main wiring and a barrier film. The linear expansion coefficient of each of the main wiring and the barrier film is larger than that of each of the insulator layers. The melting point of each of the main wiring and the barrier film is lower than that of each of the insulator layers.

Abstract: A semiconductor device includes a substrate in which a cell region and contact regions located at both sides of the cell region are defined, a first source layer formed over the substrate, a second source layer formed over the first source layer, a reinforcement pattern formed in the second source layer, a stacked structure including conductive layers and insulating layers alternately stacked over the second source layer and the reinforcement pattern, channel layers passing through the stacked structure and the second source layer and electrically coupled to the second source layer, and an isolation insulating pattern passing through at least one top conductive layer of the conductive layers.

Abstract: A light-emitting device comprises: a first semiconductor layer; a transparent conductive oxide layer including a diffusion region having a first metal material and a non-diffusion region devoid of the first metal material, wherein the non-diffusion region is closer to the first semiconductor layer than the diffusion region; and a metal layer formed on the transparent conductive oxide layer, wherein the metal layer is pervious to a light emitted from the active layer and comprises a pattern.

Abstract: In a cell region of a first major surface of a semiconductor substrate of a first conductivity type, a first well of a second conductivity type is in an upper surface. A diffusion region of a first conductivity type is in the upper surface in the first well. A first gate insulating film is on the first well, and a first gate electrode on the first gate insulating film. A second well of a second conductivity type is in the upper surface of the first major surface on a peripheral portion of the cell region. A second gate insulating film is on the second well, and a thick field oxide film is on the peripheral side of the second gate insulating film. A second gate electrode is sequentially on the second gate insulating film and the field oxide film and electrically connected to the first gate electrode. A first electrode is connected to the first well, the second well and the diffusion region. A second electrode is connected on a second major surface of the semiconductor substrate.

Abstract: FinFET devices and methods of making the same. A structure includes: a substrate with a buried insulator, a plurality of fins over a recessed buried insulator, and a nitride material filing recessed spaces between the plurality of fins, wherein the plurality of fins remain uncovered by the nitride, and wherein the nitride material does not contact the bottom of the plurality of fins.

Abstract: Processes and overturned thin film device structures generally include a metal gate having a concave shape defined by three faces. The processes generally include forming the overturned thin film device structures such that the channel self-aligns to the metal gate and the contacts can be self-aligned to the sacrificial material.