Abstract: A memory system includes a nonvolatile memory device including a plurality of memory blocks each including a plurality of pages; and a controller suitable for, when writing a plurality of data in the pages according to a write request from a host, writing the plurality of data with tags, classified into N number of kinds depending on a usage pattern of each data, together in the pages. The controller manages a list of victim blocks as a target of a merge operation, the controller manages entire valid pages included in the victim blocks, by classifying them into N number of page groups depending on a kind of each of the entire valid pages, and the controller selects valid pages to be moved to a free block in the merge operation, among the entire valid pages, and N may be a natural number of 2 or greater.

Abstract: Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Abstract: An information processing apparatus includes a first memory, a second memory, and a processor coupled to the first memory and the second memory. The first memory is configured to store data and has a first access speed. The second memory is configured to store data and has a second access speed different from the first access speed. The processor is configured to determine respective storage destinations of first data stored in the first memory and second data stored in the second memory from among the first memory and the second memory based on a first access probability and a first latency of the first data and a second access probability and a second latency of the second data.

Abstract: A system for elastic volume type selection and optimization is provided. The system may detect that a block storage volume was provisioned by a public cloud computing platform based on a first volume type identifier of a first volume type. The system may determine, based on a normalization model, a baseline operation rate and a baseline throughput rate for the provisioned block storage volume. The system may determine, based on a selected transition mode and historical performance measurements, a simulated operation rate and a simulated throughput rate. The system may communicate, in response to the simulated throughput being greater than the baseline throughput rate or the simulated operation rate being greater than the baseline operation rate, a provisioning instruction to re-provision the provisioned block storage volume on the cloud computing platform.

Abstract: Methods, systems, and apparatus for determining whether an access bit is set for each page table entry of a page table based on a scan of the page table with at least one page table walker, the access bit indicating whether a page associated with the page table entry was accessed in a last scan period; incrementing a count for each page in response to determining that the access bit is set for the page table entry associated with the page; resetting the access bit after determining whether the access bit is set for each page table entry; receiving a request to access, from a main memory, a first page of data; initiating a page fault based on determining that the first page of data is not stored in the main memory; and servicing the page fault with a DMA engine.

Abstract: A flash memory controller includes a processing circuit which is arranged for receiving a first command and a first portion address parameter, receiving a second command and a second portion address parameter, obtaining a complete address parameter by combining the first portion address parameter with the second portion address parameter, and performing a corresponding operation upon a flash memory according to the complete address parameter and a command type of the second command.

Abstract: Aspects provide multi-tier data synchronization based on a concurrent linked monitor list. A computer processor associates each of different data regions of a packed data object with different mutual exclusion monitor nodes of a linked list, the data regions defined by a data offset location within memory data and a length of the data region from the offset. In response to determining that a first data region of the packed data object is on-heap memory, the processor associates the first data region with a container representative of the linked list sorted in ascending order of the respective offset values, and a hash code of the container; and in response to determining that a second data region of the packed data object is off-heap memory, stores container information for the second data region in the linked list and resorts the linked-list nodes of container information in ascending order of offset values.

Abstract: A code protection scheme for controlling access to a memory region in an integrated circuit includes a processor with an instruction pipeline that includes multiple processing stages. A first processing stage receives one or more instructions. A second processing stage receives address information identifying a protected memory region of the memory from the first processing stage and protection information for an identified protected memory region. The protection information indicates a protection state assigned to each protected memory region. Based on the instruction type of the received instruction and the protection information associated with a particular protected memory region, the second processing stage determines whether to enable or disable access to the particular protected memory region by the processor or other external host.

Abstract: A memory management method for a rewritable non-volatile memory module, a memory control circuit unit and a memory storage apparatus are provided. The rewritable non-volatile memory module includes a plurality of super physical units, and the super physical units at least include a plurality of good super physical units and a plurality of partial good super physical units. The method includes: receiving a host write command; selecting a first super physical unit set according a number rate of the good super physical units and the partial good super physical units, and the first super physical unit set includes a plurality of first good super physical units and at least one first partial good super physical unit selected from the super physical units according to the number rate; and writing data into the good physical erasing units of the first super physical unit set, in response to the host write command.

Abstract: Methods that can optimize data storage via tracking flashcopy use are provided. One method includes storing flashcopies of data to a target volume in which the data is stored on a source volume and each flashcopy represents a particular portion of the data. The method further includes tracking a quantity of input/output (I/O) requests for each respective portion of the data on the target volume represented by a flashcopy and copying a particular portion of the data from the source volume to the target volume in response to receiving a predetermined quantity of I/O requests on the target volume for the particular portion of the data. Systems and apparatus that can include, perform, and/or implement the methods are also provided.

Abstract: A system and method for efficient cache flushing are provided. The disclosed method includes maintaining a data structure in connection with a plurality of blocks used for data caching, the data structure including a row lock wait list section. The method further includes receiving an Input/Output (I/O) request, performing a hash search for the I/O request against the data structure, and based on the results of the hash search, locking at least one row in a data cache thereby preventing read and write operations from being performed on the at least one row until the at least one row is unlocked.

Abstract: An electronic device and a method for managing memory thereof are disclosed. According to an embodiment of the present disclosure, a method for an electronic device to manage memory, comprising: determining whether a physical address mapped to a virtual address is consecutive with respect to at least two entries belonging to a plurality of entries having virtual addresses and physical addresses mapped and including a consecutive virtual address; merging entries in which the virtual address and the physical address are consecutive into one entry if, as a result of the determination, the physical addresses of the at least entries are consecutive; and storing the merged entry in first memory.

Abstract: In some aspects, devices, systems, and methods are provided that relate to data deduplication performed in data storage devices, such as solid-state drives (SSD) or drives of any other type. In some aspects, devices, systems, and methods are provided that relate to hierarchical data deduplication at a local and system level, such as in a storage system built with one or more SSDs having built-in data deduplication functionality. The hierarchical data deduplication utilizes the IDs in the data storage devices to decide if the incoming data has to be stored or if a copy of the incoming data is already stored. In hierarchical data deduplication, no IDs (or signatures) are required to be stored at a system level. In some aspects, data steering is provided that enables data storing coordination in a system that consists of a set of data storage device (e.g., SSDs) having built-in data deduplication.

Abstract: Exposing a proprietary image backup to a hypervisor as a disk file that is bootable by the hypervisor. In one example embodiment, a method of exposing a proprietary image backup to a hypervisor as a disk file that is bootable by the hypervisor may include identifying the proprietary image backup having a proprietary format and storing an operating system, identifying a plugin file corresponding to the proprietary image backup, gathering operating system data from the proprietary image backup, reformatting the operating system data into a native format of the hypervisor, and booting the operating system in a guest virtual machine of the hypervisor.

Abstract: A heterogeneous computing system includes a first processor and a second processor that are heterogeneous. The second processor is configured to sequentially execute a plurality of kernels offloaded from the first processor. A coherency controller is configured to classify each of the plurality of kernels into one of a first group and a second group, based on attributes of instructions included in each of the plurality of kernels before the plurality of kernels are executed and is further configured to reclassify one of the plurality of kernels from the second group to the first group based on a transaction generated between the first processor and the second processor during execution of the one of the plurality of kernels.

Abstract: An embodiment of a memory apparatus may include a tag cache to cache tag information, and a memory controller communicatively coupled to the tag cache to determine if a request for a memory line results in a tag cache miss, bring tag information for the missed memory line into the tag cache if the request results in a cache miss, and bring tag information for at least one additional memory line adjacent to the missed memory line into the tag cache if the request results in a cache miss. Additional embodiments are disclosed and claimed.

Abstract: Methods, systems, and computer readable media for execution by a cloud storage system are provided. One example method is for storage processing on a cloud system. The method includes executing a storage application on a compute node of the cloud system, and the storage application is configured to process write commands and read commands to and from storage of the cloud system. The write commands and the read commands are from an application. The method includes processing, by the storage application, a write command from the application. The processing includes writing data blocks to memory cache provided by the compute node for the storage application; writing data blocks written to memory cache to a write cache of a block storage that is part of the storage of the cloud system; and writing select data blocks written to memory cache to a read cache of block storage that is part of storage of the cloud system.

Abstract: A memory management method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving a first write command and writing data corresponding to the first write command into a first spare physical erasing unit; detecting an amount of second spare physical erasing units excluding the first spare physical erasing unit; determining whether the amount of the second spare physical erasing units is less than a threshold value; and performing a first procedure if the amount of the second spare physical erasing units is less than the threshold value. The first procedure includes: moving valid data in the physical erasing units into at least one third spare physical erasing unit; and adjusting the threshold value from a first threshold value to a second threshold value.

Abstract: A method includes monitoring a request rate of speculative memory read requests from a penultimate-level cache to a main memory. The speculative memory read requests correspond to data read requests that missed in the penultimate-level cache. A hit rate of searches of a last-level cache for data requested by the data read requests is monitored. Core demand speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding core demand data read request based on the request rate and the hit rate. Prefetch speculative memory read requests to the main memory are selectively enabled in parallel with searching of the last-level cache for data of a corresponding prefetch data read request based on the request rate and the hit rate.

Abstract: A funnel locking technique for normal read-copy update (RCU) grace period requests. Based on a calculated future normal RCU grace period, a traversal is initiated of a funnel lock embodied as a hierarchical tree of nodes. The funnel-lock traversal starts at an initial node whose lock is held throughout the funnel-lock traversal. For each node accessed during the funnel-lock traversal that is not the initial node, a lock on the node is held while accessing that node. For each accessed node, the funnel-lock traversal is terminated if the future normal RCU grace period has already been requested at that node, if the node believes that the future normal RCU grace period as already started, or if the node is not the initial node and believes that any normal RCU grace period is underway. Otherwise, a request for the future normal RCU grace period is recorded at the node.