Patents Examined by Gary J. Portka
  • Data storage device and operating method for dynamically executing garbage-collection process
    Patent number: 10592412
    Abstract: A data storage device for dynamically executing the garbage-collection process is provided which includes a flash memory and a controller. The flash memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the flash memory and is utilized to execute the garbage-collection process on the flash memory according to a number of at least one spare block in the flash memory and the number of non-spare blocks corresponding to different ratios of effective pages. The garbage-collection process is utilized for merging at least two non-spare blocks to release at least one spare block.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: March 17, 2020
    Assignee: SILICON MOTION, INC.
    Inventor: Kuan-Yu Ke
  • Memory system and method for controlling nonvolatile memory
    Patent number: 10592409
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Data storage system comprising primary and secondary storage systems
    Patent number: 10585764
    Abstract: Data is stored on a primary storage system and a copy of the data is stored on a secondary storage system. A determination is made that a connection between the systems is currently unavailable. Location data is maintained that identifies where changes have been made to the primary storage system while the connection is unavailable. Another determination is made that data has been lost at the secondary storage system. Recovery data required to repair the lost data is identified. Another determination is made that the connection to the secondary storage system is now available. The location data is updated with the locations of the recovery data. The secondary storage system is updated with data from the primary storage system as defined by the location data.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: March 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ian Boden, John P. Agombar, Gordon Hutchison, Lee J. Sanders
  • Ordering of memory device mapping to reduce contention
    Patent number: 10585791
    Abstract: An embodiment of a semiconductor apparatus may include technology to determine a differentiator associated with an access request for two or more memory devices, and set a target order for the two or more memory devices based on the differentiator. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 10, 2020
    Assignee: Intel Corporation
    Inventors: Yu Du, Ryan Norton, David J. Pelster, Xin Guo
  • Multi-ring shared, traversable, and dynamic advanced database
    Patent number: 10579520
    Abstract: Examples of the present disclosure describe systems and methods for sharing memory using a multi-ring shared, traversable and dynamic database. In aspects, the database may be synchronized and shared between multiple processes and/or operation mode protection rings of a system. The database may also be persisted to enable the management of information between hardware reboots and application sessions. The information stored in the database may be view independent, traversable, and resizable from various component views of the database. In some aspects, an event processor is additionally described. The event processor may use the database to allocate memory chunks of a shared heap to components/processes in one or more protection modes of the operating system.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: March 3, 2020
    Assignee: Webroot Inc.
    Inventor: John R. Shaw, II
  • Memory channel storage device initialization
    Patent number: 10558468
    Abstract: Technologies are disclosed herein that allow for utilization of memory channel storage (“MCS”) devices in a computing system. The address range for the MCS device may be reserved during an initial boot phase of the computing system, even if the MCS is not fully accessible during the initial boot phase, due to storage of prior MCS address data in non-volatile memory. If changes to the address are detected in a later boot phase, the stored information may be updated and a reboot requested.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 11, 2020
    Assignee: American Megatrends International, LLC
    Inventors: Senthamizhsey Subramanian, Bejean David Mosher
  • Power consumption management for communication bus
    Patent number: 10558254
    Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to receive data for a current write operation to a memory, determine a number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory and in response to a determination that the number of bits in the received data for the current write operation to the memory which have changed from a previous write operation to the memory exceeds a threshold, to toggle a plurality of bits in the data for the current write operation to create an encoded data set and set an indicator bit to a value which indicates that the plurality of bits have been toggled. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: February 11, 2020
    Assignee: INTEL CORPORATION
    Inventors: Abhishek R. Appu, Altug Koker, Eric J. Hoekstra, Kiran C. Veernapu, Prasoonkumar Surti, Vasanth Ranganathan, Kamal Sinha, Balaji Vembu, Eric J. Asperheim, Sanjeev S. Jahagirdar, Joydeep Ray
  • Data storage space recovery
    Patent number: 10552041
    Abstract: A write request for the data object is received. The data object is stored at one or more of a plurality of storage nodes according to the write request. A storage manager catalog that maps a data object identification (DOID) for the data object is updated with an actual storage location of the data object, the DOID for a corresponding data object being calculated based on content of the data object, a plurality of data objects being organized into one or more storage volumes. The storage manager catalog includes a count of a number of instances of a data object that is currently referenced for each of the one or more storage volumes.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: February 4, 2020
    Assignee: eBay Inc.
    Inventors: Vinay Pundalika Rao, Mark S. Lewis, Anna Povzner
  • Allocation of heat-tiered storage among throttling units
    Patent number: 10552051
    Abstract: A data storage system has multiple tiers of data storage including an upper tier having a lower access latency and a lower tier having a higher access latency. A storage controller of the data storage system implements throttling limits regulating access to data in the data storage system for a plurality of throttling units sharing the data storage system. The storage controller also tracks access frequencies of extents in the data storage system. The storage controller migrates extents among the multiple tiers based on the access frequencies of the extents and the throttling limits implemented for the throttling units.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ashwin M. Joshi, Rahul M. Fiske, Sandeep R. Patil, Sasikanth Eda
  • Data processor
    Patent number: 10552347
    Abstract: A data processor includes an access target with the address assigned to a memory space, an access subject that gains access to the access target while specifying address, identifier, and access type, and a memory protection resource including an associative memory to perform an access control. The memory protection resource includes a plurality of entries, each including a region setting unit, an identifier determination information unit, and an attribute setting unit. When the address specified by the access subject at the access is included in the region set in the region setting unit in the entry, the identifier agrees with at least one of the identifiers specified according to the identifier determination information, and the specified access type agrees with the access type set in the attribute setting unit, the memory protection resource permits the access.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Adachi, Yoichi Yuyama
  • Providing high availability to client-specific applications executing in a storage system
    Patent number: 10545676
    Abstract: Deploying client-specific applications in a storage system utilizing redundant system resources, including: identifying a redundant controller in the storage system, wherein the storage system includes at least a first controller and the redundant controller; and executing one or more applications on the redundant controller, wherein the one or more applications are executed in a container.
    Type: Grant
    Filed: October 9, 2017
    Date of Patent: January 28, 2020
    Assignee: Pure Storage, Inc.
    Inventors: John Colgrove, Lydia Do, Ethan Miller, Terence Noonan
  • Storage device, user device including storage device, and operation method of user device
    Patent number: 10528259
    Abstract: Disclosed is a storage device which includes a nonvolatile memory device and a controller. The controller communicates with a host through a first port, communicates with an external storage device through a second port, and controls the nonvolatile memory device based on first mapping information. The controller is configured to receive second mapping information from the external storage device, receive first write data from the host and to selectively transmit first write data to the external storage device based on the second mapping information.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: January 7, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Youngmin Lee, Ji-Seung Youn, Sungho Seo, Hyuntae Park, Hwaseok Oh, JinHyeok Choi
  • Apparatus and method for managing bounded pointers
    Patent number: 10528490
    Abstract: An apparatus and method are provided for managing bounded pointers. The apparatus has processing circuitry to execute a sequence of instructions, and a plurality of storage elements accessible to the processing circuitry, for storage of bounded pointers and non-bounded pointers. Each bounded pointer has explicit range information associated therewith indicative of an allowable range of memory addresses when using the bounded pointer. A current range check storage element is then used to store a current range check state for the processing circuitry. When the current range check state indicates a default state, the processing circuitry is responsive to execution of a memory access instruction identifying a pointer to be used to identify a memory address, to perform a range check operation to determine whether access to that memory address is permitted.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: January 7, 2020
    Assignee: ARM Limited
    Inventor: Graeme Peter Barnes
  • Storage apparatus and storage control apparatus
    Patent number: 10521131
    Abstract: A storage apparatus of the present disclosure includes a plurality of storing units having different life times, and a processor configured to manage a data block to be stored in the plurality of storing units. The processor is configured to determine or infer an access characteristic for the data block, and store the data block in a storing unit in accordance with the determined or inferred access characteristic, among the plurality of storing units having the different life times. This enables to extend the life times of the storing units.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: December 31, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Kazuhiko Yamamoto
  • Hash table-based mask length computation for longest prefix match caching
    Patent number: 10515015
    Abstract: A data packet is received in a network element. The network element has a cache memory in which cache entries represent a portion of addresses stored in a main memory, The destination address and the cache entries each comprise a binary number. A hash function is applied to the masked destination address to access a hash table. When the number of most significant bits corresponding to the value in the hash table in one of the cache entries and in the destination address are identical, routing information for the packet is retrieved from the cache entry.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: December 24, 2019
    Assignee: MELLANOX TECHNOLOGIES TLV LTD.
    Inventors: Gil Levy, Aviv Kfir, Salvatore Pontarelli, Pedro Reviriego
  • Method for operating a microcontroller
    Patent number: 10503666
    Abstract: A method for operating a microcontroller, where access rights of processes executed in the microcontroller to different memory areas are stored in a memory protection unit, includes, in the course of a simulation mode, a first process carrying out an access attempt to a certain memory area in a certain manner in the name of a second process; the memory protection unit transferring access rights of the second process for the certain memory area to the first process upon the access attempt. The access rights are read out by the first process and the simulation mode is terminated. The access attempt is preferably thereupon terminated and an access is not carried out according to this access attempt by the first process.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: December 10, 2019
    Assignee: Robert Bosch GmbH
    Inventors: Jens Gladigau, Simon Hufnagel
  • Data protection using change-based measurements in block-based backup
    Patent number: 10496323
    Abstract: Data protection using change-based measurements in block-based backup is disclosed. Block change information indicating an extent of change associated with a volume may be determined. The block change information may be based at least in part on stored information indicating monitored changes to blocks in the volume. A backup operation may be initiated based at least in part on the determined block change information.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 3, 2019
    Assignee: EMC IP Holding Company LLC
    Inventors: Shelesh Chopra, Vladimir Mandic
  • Method and system for leveraging non-uniform miss penality in cache replacement policy to improve processor performance and power
    Patent number: 10496551
    Abstract: Method, system, and apparatus for leveraging non-uniform miss penalty in cache replacement policy to improve performance and power in a chip multiprocessor platform is described herein. One embodiment of a method includes: determining a first set of cache line candidates for eviction from a first memory in accordance to a cache line replacement policy, the first set comprising a plurality of cache line candidates; determining a second set of cache line candidates from the first set based on replacement penalties associated with each respective cache line candidate in the first set; selecting a target cache line from the second set of cache line candidates; and responsively causing the selected target cache line to be moved from the first memory to a second memory.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: December 3, 2019
    Assignee: Intel Corporation
    Inventors: Binh Q. Pham, Ren Wang
  • Managing data in storage systems
    Patent number: 10481820
    Abstract: A method is used in managing data in storage systems. A request is received to write data. A determination is made as to whether the data associated with the request can be relocated to a storage tier of a set of storage tiers based on a policy. The set of storage tiers includes first and second storage tiers. The first and second storage tiers are configured such that performance characteristics associated with the first storage tier is different from the second storage tier. Relocation of the data is managed to the storage tier of the set of storage tiers.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: J. Michael Dunbar
  • Accessing encoded blocks of data in memory
    Patent number: 10466915
    Abstract: A method of storing encoded blocks of data in memory comprises generating headers for the encoded blocks of data. The headers are stored in memory according to a tiled layout based on tiles of plural adjacent blocks of data elements of the array of data elements. Respective sets of the encoded blocks of data are also stored in respective distinct regions of memory locations that have been allocated to those sets. The method provides an efficient way to access headers and corresponding encoded blocks of data in memory.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: November 5, 2019
    Assignee: Arm Limited
    Inventors: Quinn Carter, Lars Oskar Flordal, Jakob Axel Fries