Abstract: A system and method include a distributed virtual tape library node on a distributed computing system node and using a distributed computing system distributed file system to manage data on multiple nodes of the distributed computing system to form a distributed virtual tape library system. A master virtual tape library on a distributed computing system node, multiple slave virtual tape library on a different distributed computing system node, and a distributed computing system distributed file system to manage data on the master and slave virtual tape libraries form a distributed virtual tape library system.

Abstract: Data of a vector storage request pertaining to one or more disjoint, non-adjacent, and/or non-contiguous logical identifier ranges are stored contiguously within a log on a non-volatile storage medium. A request consolidation module modifies one or more sub-requests of the vector storage request in response to other, cached storage requests. Data of an atomic vector storage request may comprise persistent indicators, such as persistent metadata flags, to identify data pertaining to incomplete atomic storage requests. A restart recovery module identifies and excludes data of incomplete atomic operations.

Abstract: A processor is described that includes a plurality of processing cores. The processor includes an interconnection network coupled to each of said processing cores. The processor includes snoop filter logic circuitry coupled to the interconnection network and associated with coherence plane logic circuitry of the processor. The snoop filter logic circuitry contains circuitry to hold information that identifies not only which of the processing cores are caching specific cache lines that are cached by the processing cores, but also, where in respective caches of the processing cores the cache lines are cached.

Abstract: Systems and methods are provided for an asynchronous data replication system in which the remote replication reduces bandwidth requirements by copying deduplicated differences in business data from a local storage site to a remote, backup storage site, the system comprising: a local performance storage pool for storing data; a local deduplicating storage pool for storing deduplicated data, said local deduplicating storage pool further storing metadata about data objects in the system and which has metadata analysis logic for identifying and specifying differences in a data object over time; a remote performance storage pool for storing a copy of said data, available for immediate use as a backup copy of said data to provide business continuity to said data; a remote deduplicating storage pool for storing deduplicated data; and a controller for synchronizing the remote performance storage pool to have the second version of the data object using deduplicated data.

Abstract: A semiconductor device comprises: a read queue configured to store one or more read requests to a semiconductor memory device; a write queue configured to store one or more write requests to the semiconductor memory device; and a dispatch block configured to determine a scheduling order of the one or more read requests and the one or more write requests and switch to the read queue or to the write queue if a request exists in a Row Hit state in the read queue or in the write queue.

Abstract: A host based caching technique may be used to determine caching policies for a hybrid hard disk drive. Because the host based caching may make use of knowledge about what data is being cached, improved performance may be achieved in some cases.

Abstract: A control circuit includes a ROM suitable for generating ROM data based on a ROM address corresponding to a predetermined operation, a command analyzing unit suitable for outputting the ROM address corresponding to the predetermined operation, generating an address storing signal in response to an operation suspension command for suspending the predetermined operation, and generating an address output signal in response to an operation resumption command for resuming the predetermined operation, an address storing unit suitable for storing a ROM address, which corresponds to the ROM address at a time point where the predetermined operation is suspended, in response to the address storing signal, and an address output unit suitable for outputting the ROM address corresponding to said time point in response to the address output signal, wherein the ROM generates ROM data for resuming the predetermined operation based on the ROM address corresponding to said time point.

Abstract: In accordance with an aspect of the present invention, a method and system for parallel computing is provided, that reduces the time necessary for the execution of program function. In order to reduce the time needed to execute aspects of a program, multiple program threads are executed simultaneously, while thread 0 of the program is also executed. These threads are executed simultaneously with the aid of at least one cache of the computing device on which the program is being run. Such a framework reduces wasted computing power and the time necessary to execute aspects of a program.

Abstract: Systems and methods are disclosed for configuring a non-volatile memory (“NVM”). In some embodiments, each block of the NVM can include a block table-of-contents (“TOC”), which can be encoded (e.g., run-length encoded) and dynamically-sized. Thus, as user data is being programmed to a block, the size of a block TOC can be concurrently recalculated and increased only if necessary. In some embodiments, the NVM interface can use a weave sequence stored in the context information and at least one weave sequence associated with each page of a block to determine whether to replay across the pages of the block after system boot-up.

Abstract: Systems and methods for memory page offloading in multi-processor computer systems. An example method may comprise: detecting, by a computer system, a memory pressure condition on a first node; invalidating a page table entry for a memory page residing on the first node; copying the memory page to a second node; and updating the page table entry for the memory page to reference the second node.

Abstract: For read based temporal locality compression by a processor device in a computing environment, read operations are monitored, traced, and/or analyzed to identify repetitions of read patterns of compressed data. The compressed data is rearranged based on the repetitions of read order of the compressed data that are in a read order.

Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: The disclosed embodiments provide a system that filters pre-fetch requests to reduce pre-fetching overhead. During operation, the system executes an instruction that involves a memory reference that is directed to a cache line in a cache. Upon determining that the memory reference will miss in the cache, the system determines whether the instruction frequently leads to cache misses. If so, the system issues a pre-fetch request for one or more additional cache lines. Otherwise, no pre-fetch request is sent. Filtering pre-fetch requests based on instructions' likelihood to miss reduces pre-fetching overhead while preserving the performance benefits of pre-fetching.

Abstract: A storage apparatus comprises a storage controller and multiple storage devices. The storage controller sends, to either a storage device which is a copy source of copy-target data, or a storage device which is a copy destination of the copy-target data, a copy indication showing areas of the copy source and the copy destination, and the storage device, which receives the copy indication, copies data of the copy-source area to the copy-destination area based on the copy indication without going through the storage controller.

Abstract: A data storage device and an operating method for a FLASH memory are disclosed. The disclosed data storage device includes a FLASH memory and a controller. The FLASH memory provides a storage space which is stored with a first storage type system information and a second storage type system information. Data recognition for the first storage type system information is stricter than that of the second storage type information. The controller reads the storage space of the FLASH memory and performs an error checking and correction process on data read from the storage space, and, based on the storage type system information, among the first and second storage type information, which first passes the error checking and correction process, the controller operates the FLASH memory.

Abstract: This disclosure provides techniques and apparatuses to enable early, run-ahead handling of IC and ITLB misses by decoupling the ITLB and IC tag lookups from the IC data (instruction bytes) accesses, and making ITLB and IC tag lookups run ahead of the IC data accesses.

Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.

Abstract: Methods and apparatus for facilitating pre-read and/or post-read operations of a disk drive. A write command is received including a logical block address (LBA) for user data in the write command. Parity data for correcting the user data is generated by encoding the LBA with the user data. The parity data is written on a disk of the disk drive with the user data so that the LBA can be recovered using the parity data when read from the disk. When a read command is received by the disk drive, requested user data is read from a first sector. User data and parity data is read from a second sector adjacent the first sector. The parity data is used to recover an LBA for the second sector and it is determined whether to store the user data read from the second sector based on the recovered LBA.

Abstract: A method and system for accessing a single port multi-way cache includes an address multiplexer that simultaneously addresses a set of data and a set of program instructions in the multi-way cache. Duplicate output way multiplexers respectively select data and program instructions read from the cache responsive to the address multiplexer.