Abstract: Techniques and mechanisms handle transactions between various components of a memory controller. For example, a memory controller may include a component implemented in configurable logic and another component implemented in hard logic.

Abstract: Embodiments of the present invention disclose a method and an apparatus for controlling memory startup, and relate to the field of memory control technologies. The present invention is not limited to the number of pins of a control chip, thereby reducing costs. The method is applied to a control apparatus, where the control apparatus includes a preset data segment; the preset data segment includes at least one sub data segment; and each sub data segment is corresponding to one configuration type. The method includes: reading each sub data segment in a first data segment and performing a first operation on a sub data segment corresponding to a first configuration type to obtain a second data segment; performing matching between the second data segment and the preset data segment; and starting up the memory according to the first configuration type when the second data segment matches the preset data segment.

Abstract: Software that performs the following steps: (i) collecting a set of sampling value(s), where each sampling value of the set of sampling value(s) respectively corresponds to an amount of overprovisioning-related data stored in a non-volatile memory device (NVMD) at the time the corresponding sampling value is collected; and (ii) determining an overprovisioning ratio for use with the NVMD based, at least in part, on the set of sampling value(s). The overprovisioning-related data is any data stored in overprovisioning space as a result of overprovisioning-type operations.

Abstract: The present invention provides systems and methods for data storage. A hierarchical storage management architecture is presented to facilitate data management. The disclosed system provides methods for evaluating the state of stored data relative to enterprise needs by using weighted parameters that may be user defined. Also disclosed are systems and methods evaluating costing and risk management associated with stored data.

Abstract: A digital Storage Element is described. A device is configured including a Storage Element for access by a user responsive to a native control code. A processing arrangement executes a control program for controlling the overall device and executing at least a portion of the native control code as part of the control program for interfacing with the Storage Element. A programming arrangement is provided separate from the device for customizing a read channel within the Storage Element. Command, user interaction and data transfer execution are discussed for mitigation of potential mechanical shock effects. Status indications relating to the Storage Element are provided including head position and mechanical shock. Calibration, test and operational monitoring procedures, for using head position status, are described. Failure configuration monitoring is provided in tracking overall performance and design considerations.

Abstract: Disclosed herein are system, method and/or computer program product embodiments for automatically resuming an irregular erasure stoppage in a sector of a memory system. An embodiment includes storing information related to any completed sub-stage of a multi stage erasure process and the corresponding memory sector address in a dedicated memory. After an irregular erasure stoppage occurs, an embodiment reads the information from the dedicated memory and resumes the erasure process of the memory sector from the last sub-stage completed.

Abstract: In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.

Abstract: A signal control circuit includes: a delay acquisition circuit configured to obtain a first delay amount to be added to an input signal for aligning timing of rise of the input signal with timing of fall or rise of a reference signal and a second delay amount to be added to the input signal for aligning timing of fall of the input signal with timing of the fall or the rise of the reference signal; and a ratio calculation circuit configured to calculate a duty ratio of the input signal based on a difference between the first delay amount and the second delay amount.

Abstract: A virtual address pager and method for use with a bulk erase memory is disclosed. The virtual address pager includes a page protection controller configured with a heap manager interface configured to receive only bulk erase memory-backed page requests for a plurality of memory pages. A RAM object cache controller is configured to store and bulk write data for a portion of the bulk erase memory. The page protection controller may have an operating system interface configured to generate a page memory access permission for each of the plurality of memory pages. The page protection controller may be configured to receive a virtual memory allocation request and generate the page memory access permission based on the virtual memory allocation request.

Abstract: A processor includes: a primary cache memory; an instruction control unit that issues a store request to the primary cache memory; a pipeline processing unit that, upon receiving the store request, writes data to the primary cache memory; a buffer unit that obtains an address output to the primary cache memory from the pipeline processing unit during an output period of the store request regarding certain data to hold the obtained address in an entry, and when the output period ends, issues a write-back request for writing the data indicated by the address held in the entry to a memory; and a secondary cache memory that, upon receiving the write-back request from the buffer unit, writes the data of the primary cache memory to the memory, the certain data is quickly written back to the memory from the primary cache memory.

Abstract: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. The cache includes cache entries organized in a first list of cache entries and a second list of cache entries. Only a portion of all cache entries from the first and second lists is selected for migration to the second storage device. The selected cache entries and metadata for cache entries from the first or second list that were not selected are migrated from the first storage device to the second storage device.

Abstract: A method is described that includes performing the following for a transactional operation in response to a request from a processing unit that is directed to a cache identifying a cache line. Reading the cache line, and, if the cache line is in a Modified cache coherency protocol state, forwarding the cache line to circuitry that will cause the cache line to be written to deeper storage, and, changing another instance of the cache line that is available to the processing unit for the transactional operation to an Exclusive cache coherency state.

Abstract: A storage system and method for interleaving a plurality of logical sectors in the storage system is disclosed. The method includes: dividing each logical sector into a predetermined number of slices; sequentially indexing the logical sectors, wherein each logical sector is identified by a logical sector index; sequentially indexing the predetermined number of slices in each logical sector, wherein each slice of the predetermined number of slices is identified by a slice index within each logical sector; and interleaving the logical sectors according to a slice interleaving process. The interleaving step further includes: a) identifying a first indexed slice of a first indexed logical sector as an initial slice; and b) identifying a subsequent slice by advancing the slice index to a subsequent index in the slice index sequence and advancing the logical sector index to a subsequent index in the logical sector index sequence.

Abstract: Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.

Abstract: For nonvolatile random access memory (NVRAM) use, a query module identifies persistent data on a NVRAM in response to waking the NVRAM. A management module makes available the persistent data for use.

Abstract: Embodiments include multi-processor systems, including multi-core processor systems, as well as methods for operating the same, in which at least one processor or processor core is configured to receive an instruction directing the at least one processor core to read a value associated with a memory address. In response to receiving the instruction and before execution of the instruction, the at least one processor or processor core causes ones of the plurality of mutually communicatively inter-coupled processor cores to provide a plurality of locally stored values that are stored individually in the respective processor cores and that are associated with the memory address.

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

Abstract: Exemplary methods, apparatuses, and systems determine that a cache is to be migrated from a first storage device to a second storage device. Each cache entry within the cache includes a first indicator to indicate whether or not the cache entry has long-term utility. Only a portion of all cache entries are selected to be migrated and the portion is selected from cache entries with the first indicator set to indicate long-term utility. The selected cache entries and metadata for cache entries that were not selected are migrated from the first storage device to the second storage device.

Abstract: A method for migrating data in a tiered storage architecture is disclosed. In one embodiment, such a method includes tracking the temperature of data blocks in a tiered storage architecture, where the temperature indicates the frequency the data blocks are accessed. Heat maps are generated that indicate the temperature of the data blocks across different time intervals. These heat maps are compared to identify temperature patterns that may occur over time. The temperature patterns, in turn, may be used to predict when selected data blocks will change in temperature. Data blocks may be migrated between tiers of the tiered storage architecture in anticipation of the predicated changes in temperature. A corresponding system and computer program product are also disclosed.

Abstract: According to one embodiment, a storage device includes a first memory, an interface that includes first physical layers and connects a host and the first memory, a second memory that temporarily stores the data transferred between the host and the first memory, a controller that controls operation of the interface. When the data is transferred from the first memory to the host, the controller reads the data corresponding to the data transfer request into the second memory, the controller selects the physical layer to transfer the data from the second memory to the host based on a first period until the data is ready for transmission after data transfer is requested.