Patents Examined by Gayathri Sampath
  • Patent number: 9230112
    Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.
    Type: Grant
    Filed: February 23, 2013
    Date of Patent: January 5, 2016
    Assignee: XILINX, INC.
    Inventors: Edward S. Peterson, Roger D. Flateau, Jr., James D. Wesselkamper, Steven E. McNeil, Jason J. Moore, Lester S. Sanders, Lawrence C. Hung, Yatharth K. Kochar
  • Patent number: 9223376
    Abstract: A method and system for managing electrical current within a portable computing device (“PCD”) includes assigning a priority to two or more communications supported by the PCD. A present level of a power supply for the PCD may be monitored by a communications power (“CP”) manager module. Next, the CP manager module may determine if the two or more communications may be transmitted at the present level of the power supply. If the two or more communications cannot be transmitted at the present level of the power supply, then the CP manager module may determine if a timing of at least one of the communications may be adjusted. The CP manager module may also determine a theoretical power level adjustment for at least one of the communications. The two or more communications may be transmitted with any calculated timing off sets and power level adjustments.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 29, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Amy Derbyshire, Francis Ngai, Ali Taha, Eric Mikuteit, Michael Lee McCloud, Amit Mahajan, David Coronel, Prashanth Akula, Todd Sutton, Hardik Patel, Hector Corleto
  • Patent number: 9213552
    Abstract: A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: December 15, 2015
    Assignee: Vision Works IP Corporation
    Inventor: Beau M. Braunberger
  • Patent number: 9195297
    Abstract: A bridging device and a power saving method thereof are disclosed. The disclosed bridging device includes a connector, a connection detector and a bridging chip. The connector is operative to connect to a host and includes a power pin and a command pin. The connection detector is coupled to the power pin to determine whether the connector is floating, and, outputs a linked signal when the connection is non-floating. The bridging chip is coupled to the command pin and the connection detector. When the bridging chip receives a power saving command transferred from the host via the command pin and the linked signal transferred from the connection detector, the bridging chip executes a power saving operation.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: November 24, 2015
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Wei-Hung Chen, Hui-Chih Lin
  • Patent number: 9197949
    Abstract: An appliance network connectivity apparatus includes a voltage sensor that generates a signal at an output that is proportional to a voltage provided to the appliance. A current sensor generates a signal at an output that is proportional to a current flowing through the appliance. A processor determines the electrical characteristics of power consumed by the appliance and executes web server software for communicating data through a network. A relay controls power from the power source to the appliance. A memory stores the electrical characteristics. A network interface provides the electrical characteristics to the network.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: November 24, 2015
    Assignee: Tenrehte Technologies, Inc.
    Inventors: Mark Allen Indovina, Jennifer Marie Indovina, Russell Dean Priebe, Carlos Antonio Barrios, Steven Lee Boggs
  • Patent number: 9176554
    Abstract: Methods and apparatus relating to robust governing of power management infrastructure in a bridge design are described. In one embodiment, a first agent (such as a processor core) is coupled to a second agent (such as an input/output device) via a bridge. The bridge may or may not enter a different power management state from a current power management state based on a second derivative value. The second derivative value may be in turn determined based on a plurality of first derivative values corresponding to received packets Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2012
    Date of Patent: November 3, 2015
    Assignee: Intel Corporation
    Inventor: Poh Thiam Teoh
  • Patent number: 9170602
    Abstract: A method is used in calibrating an internal clock generator. An electronic device is instructed to output a high-speed clock signal which is communicated to an external calibration system. The high-speed clock signal is measured using measurement equipment associated with the external calibration system. One or more calibration values based on the measured clock signal value are calculated. The calculated calibration values are communicated to the electronic device. The electronic device is instructed to generate a calibrated clock signal by applying the one or more calibration values to an internally generated clock signal.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 27, 2015
    Assignee: EMC Corporation
    Inventors: Joseph M. Pirrotta, Marco Ciaffi
  • Patent number: 9158330
    Abstract: Methods and apparatuses for processing systems capable of compensating for data skew are disclosed. An example apparatus can include delay circuitry that includes a plurality of delay devices each being individually adjustable to produce an individual delay for each data line with each data line including branches of different lengths leading to different memory devices, and memory control circuitry coupled to the delay circuitry and configured to determine, for each data line, an individual delay based on an optimized critical window, the optimized critical window being based on multiple chip select signals.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: October 13, 2015
    Assignee: Marvell Israel (M.I.S.L) LTD.
    Inventors: Eldad Bar-Lev, Aaron Landau
  • Patent number: 9160348
    Abstract: A processor arrangement changes its default time interval for entering a power saving mode based on sensed operating conditions and predetermined time intervals to be used under various operating conditions to optimize power saving.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: October 13, 2015
    Assignee: Broadcom Corporation
    Inventor: Hwisung Jung
  • Patent number: 9152217
    Abstract: An information processing apparatus capable of reducing time taken to return to a standby state after turn-off of a power switch in a power saving state. A power supply supplies power to a CPU and a RAM in a standby state, supplies power to the RAM without supplying power to the CPU in a second waiting state caused by turning off the power switch, and supplies power to the RAM without supplying power to the CPU in the power saving state caused without having the power switch turned off when a shift-to-power saving state requirement defined in advance is satisfied. A power supply controller causes the apparatus to shift from the second waiting state to the standby state using a standby memory image. The CPU writes the standby memory image in the RAM for storage in the power saving state.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 6, 2015
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Koji Shimizu
  • Patent number: 9141172
    Abstract: A method and apparatus to control and manage a power state in a related set of storage devices is described. In one example a method includes, determining an idleness measure at the file system, the idleness measure indicating availability requirements of the device set, and setting an idle state based on the idleness measure. The method also includes receiving the idle state setting at the storage subsystem, determining whether the idle state setting is different from a current state of the device set, determining whether to change the idle state of the device set if the idle state setting is different from the current state of the device set, the determining being based on information about the device set. The method also includes commanding the device set to change the current idle state to correspond to the idle state setting based on determining whether to change the idle state.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: September 22, 2015
    Assignee: EMC Corporation
    Inventors: Andrew W. Leung, Kevin M. Greenan, Windsor W. Hsu
  • Patent number: 9134777
    Abstract: Systems and methods for bi-modal and fine grained power delivery to an integrated circuit comprising functional blocks. A first power source is coupled to a functional block of the integrated circuit for supporting a first operating mode of the functional block. A second power source is coupled to the functional block for supporting a second operating mode of the functional block. The first and second operating modes can be high and low frequency modes respectively. The second power source can be derived from the first power source using on-die regulators or provided independently. A desired average throughput of the functional block can be achieved by controlling duty cycles of the first and second power sources.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Yeshwant Nagaraj Kolla, Jeffrey Herbert Fischer, William R. Flederbach
  • Patent number: 9122737
    Abstract: Methods, systems, and products are provided for monitoring the temperature of a high powered computing component. The high powered computing component has a thermal sensor and the high powered computing component in thermal communication with a liquid cooled heatsink. Embodiments include determining, by a thermal monitoring module, a temperature of the thermal sensor; determining, by the thermal monitoring module, a temperature of the heatsink; determining, by the thermal monitoring module, a power delivered to the high powered computing component; and calculating, by the thermal monitoring module, a thermal value in dependence upon the temperature of the thermal sensor, the temperature of the heatsink, and the power delivered to the high powered computing component.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: David L. Darrington, Adam C. Emerich, Michael J. Fedor, Raymond K. Shokes
  • Patent number: 9122736
    Abstract: Methods, systems, and products are provided for monitoring the temperature of a high powered computing component. The high powered computing component has a thermal sensor and the high powered computing component in thermal communication with a liquid cooled heatsink. Embodiments include determining, by a thermal monitoring module, a temperature of the thermal sensor; determining, by the thermal monitoring module, a temperature of the heatsink; determining, by the thermal monitoring module, a power delivered to the high powered computing component; and calculating, by the thermal monitoring module, a thermal value in dependence upon the temperature of the thermal sensor, the temperature of the heatsink, and the power delivered to the high powered computing component.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 1, 2015
    Assignee: International Business Machines Corporation
    Inventors: David L. Darrington, Adam C. Emerich, Michael J. Fedor, Raymond K. Shokes
  • Patent number: 9104364
    Abstract: An indication of time that indicates at least one of the current day and the current time is received. It is determined that a raw interval pulse transmitted by a first oscillator should be adjusted based, at least partly, on the indication of time. In response to determining that the raw interval pulse should be adjusted, a steered time interval pulse is generated based, at least partly, on the raw time interval pulse and the indication of time. The steered time interval pulse is distributed to a plurality of hardware components.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: August 11, 2015
    Assignee: International Business Machines Corporation
    Inventors: Eberhard Engler, Guenter Gerwig, Willm Hinrichs, Barinjato Ramanandray
  • Patent number: 9069552
    Abstract: An image forming apparatus includes a functional unit, a first power supply circuit supplying electric power to the functional unit from a commercial power supply, a second power supply circuit including a self-generation power supply, and a third power supply circuit including a power storage unit storing electric power and a charging circuit charging the power storage unit upon receipt of supply of electric power from at least one of the commercial power supply and the self-generation power supply. In accordance with the amount of power supply from the self-generation power supply, higher priority is given to supply of electric power to the functional unit from at least one of the second and third power supply circuits than to supply of electric power from the first power supply circuit.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: June 30, 2015
    Assignee: KONICA MINOLTA BUSINESS TECHNOLOGIES, INC.
    Inventors: Hiroshi Hiraguchi, Takashi Hasebe, Tomonobu Tamura, Mineo Yamamoto, Yuhei Tatsumoto
  • Patent number: 9058173
    Abstract: A method for controlling a mobile terminal device that includes a multi-core CPU and a display that displays an execution result of an application program executed by the multi-core CPU includes detecting an application program of which an execution result is displayed, calculating a CPU load per thread in the application program detected in the detecting, and increasing the number of cores operating in the multi-core CPU when the number of threads, each of the threads causing the CPU load to be equal to or higher than a first value, is equal to or higher than a second value.
    Type: Grant
    Filed: August 23, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Takeo Murakami
  • Patent number: 9015510
    Abstract: Systems and methods may provide for aggregating a first idle duration from a first device associated with a platform and a second idle duration from a second device associated with the platform. Additionally, an idle state may be selected for the platform based at least in part on the first idle duration and the second idle duration. In one example, the idle durations are classified as deterministic, estimated or statistical.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Christian Maciocco, Ohad Falik, Ren Wang, Nadav Shulman, Paul Diefenbaugh, Tsung-Yuan Charles Tai
  • Patent number: 8984312
    Abstract: A first battery 102 is removably housed in a first battery housing unit 108, and a second battery 103 is removably housed in a second battery housing unit 110. When it is detected that a lid 107 or 109 that is used when the first battery 102 or the second battery 103 is replaced is in an open state, system control sections 113 and 114 start a restriction mode for restricting an operation of an information processing device 100 such that power consumption by the information processing device 100 is curtailed.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 17, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventor: Takashi Koshimizu
  • Patent number: 8972759
    Abstract: Various embodiments of methods and systems for adaptive thermal management techniques implemented in a portable computing device (“PCD”) are disclosed. Notably, in many PCDs, temperature thresholds associated with various components in the PCD such as, but not limited to, die junction temperatures, package on package (“PoP”) memory temperatures and the “touch temperature” of the external surfaces of the device itself limits the extent to which the performance capabilities of the PCD can be exploited. It is an advantage of the various embodiments of methods and systems for adaptive thermal management that, when a temperature threshold is violated, the performance of the PCD is sacrificed only as much and for as long as necessary to clear the violation before authorizing the thermally aggressive processing component(s) to return to a maximum operating power.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: March 3, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Paras S. Doshi, Ankur Jain, Unnikrishnan Vadakkanmaruveedu, Vinay Mitter, Anil Vootukuru, Ronald F. Alton, Jon J. Anderson