Abstract: In an embodiment, a processor includes multiple cores and a power controller. The power controller may include a hardware duty cycle (HDC) logic to cause at least one logical processor of one of the cores to enter into a forced idle state even though the logical processor has a workload to execute. In addition, the HDC logic may cause the logical processor to exit the forced idle state prior to an end of an idle period if at least one other logical processor is prevented from entry into the forced idle state. Other embodiments are described and claimed.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: File sharing circuit and computer using the same are provided. The computer includes a computer host and a file sharing circuit. The computer host includes a first storage device, a first system control chip, a control unit, and a power integrated circuit. The file sharing circuit includes a second system control chip and a first bus switch. When the second system control chip performs a file sharing procedure, the power integrated circuit powers the first storage device, the second system control chip, and the first bus switch, and the control unit switches the first bus switch to a first state so that the second system control chip accesses the first storage device. When the second system control chip does not perform the file sharing procedure, the control unit switches the first bus switch to a second state so that the first system control chip accesses the first storage device.

Abstract: In one embodiment, an electronic device comprises an oscillator configured to generate an oscillator signal, and a timing circuit configured to generate a count value based on the oscillator signal, to compare the count value with a first compare value, to determine a first expiry event upon the count value matching the first compare value, and to generate a first wakeup signal in response to the first expiry event. The electronic device also comprises a battery pass circuit configured to receive the first wakeup signal, and to couple a power source to a main device in response to the first wakeup signal to power on the main device. The electronic device further comprises a state sequencing circuit configured to store a state of the main device, and an interface circuit configured to communicate the stored state to the main device.

Abstract: It is determined that a current node power consumption for a node is greater than a node power cap that defines a limit of power consumption for the node. Responsive to the current node power consumption being greater than the node power cap and until the current node power consumption is less than the node power cap, power reduction operations are performed. The power reduction operations comprise determining a power management zone of a plurality of power management zones having a lowest priority among the power management zones and having a power cap greater than a minimum power cap for the power management zone. The power reduction operations further comprise setting the power cap for the power management zone to a value less than a prior value assigned as the power cap for the power management zone.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A computer-implemented method, computer program product, and computer system for identifying power line segments and power line redundancies in a datacenter are provided. The computer-implemented method for identifying power line segments and power line redundancies in a datacenter include; transmitting a data packet from equipment compilers to a host program, where the data packet includes unique datacenter equipment identifiers, the datacenter equipment includes IT equipment and a power source; identifying one or more power line segments from the power source to the IT equipment; and determining an existence of a power line redundancy between the power source and the IT equipment.

Abstract: A power distribution system includes a manager provided on a network controller and an agent provided on a line module. The manager is operable to receive a configuration for a port on the line module. A connection to the port is then detected by the agent and communicated to the manager. At least one of the manager and the agent determines that the connection is for a powered device that is operable to receive power and data through the port. The manager then classifies the powered device. If the manager determines that the classification of the powered device corresponds to the configuration of the port, the manager provides power to the powered device through the port according to an allocation for the powered device from a global power budget.

Abstract: A method and apparatus for optimizing a configuration memory of a reconfigurable processor is provided. The method of optimizing the configuration memory of the reconfigurable processor includes analyzing parallelism of a loop of a program code based on an architecture of the reconfigurable processor and information regarding the configuration memory, scheduling groups of function units (FUs) to be activated in each cycle of the loop based on the analyzed parallelism, generating configuration data of each cycle, and determining a memory mapping to store the generated configuration data in the configuration memory.

Abstract: A system can include a processor; memory operatively coupled to the processor; a chipset operatively coupled to the processor; ports where each of the ports includes a respective power supply line; a switch; a hub operatively coupled to the ports and to the chipset for data transfer via an in-band protocol; and a microcontroller operatively coupled to the chipset, to the switch and to the hub where the microcontroller includes circuitry that controls the switch to transfer data to one of the ports via an out-of-band protocol and where the microcontroller includes circuitry that controls supply of power to the power supply lines.

Abstract: A zone power cap for a power management zone that defines a limit of power consumption for the power management zone is determined. The power management zone comprises a plurality of components, wherein the power management zone is associated with a controller. A set of one or more characteristics of a workload associated with the power management zone is determined. A component power cap for one or more of the plurality of components is set based, at least in part, on the set of one or more characteristics of the workload and the zone power cap.

Abstract: Methods for thermal management of an integrated circuit are disclosed. In particular, a dual control loop, having a first control loop and a second control loop, is used to maintain the temperature of an integrated circuit at a first temperature and a second temperature, respectively. In order to prevent the integrated circuit from overheating during periods of rapid temperature increase, the second control loop may be configured to control temperature at the second temperature below the specification limit of the integrated circuit by reducing power to the integrated circuit. The second control loop samples and maintains temperature of the integrated circuit at time intervals relatively faster than that of the first control loop. However, the second control loop is configured to release control to the first control loop when the temperature of the integrated circuit is reduced. The first control loop may then control power to the integrated circuit.

Abstract: Methods and apparatus relating to Active State Power Management (ASPM) to reduce power consumption by PCI express components are described. In one embodiment, a special packet with embedded information triggers entry into a lower power consumption state. The embedded information may include flow control credit information outstanding between two agents and the target power consumption state. Other embodiments are also disclosed and claimed.

Abstract: Methods and apparatus relating to controlling power consumption by a power management link are described. In one embodiment, the physical interface of a power management (PM) link is shut down when a processor is in a sleep state (e.g., to conserve power), while maintaining the availability of the processor for communication to a (e.g., embedded) controller over the PM link. Other embodiments are also disclosed and claimed.

Abstract: In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Abstract: Various aspects of the present disclosure provide for a system that is able to boot from a variety of media that can be connected to the system, including SPI NOR and SPI NAND memory, universal serial bus (“USB”) devices, and devices attached via PCIe and Ethernet interfaces. When the system is powered on, the system processor is held in a reset mode, while a microcontroller in the system identifies an external device to be booted, and then copies a portion of boot code from the external device to an on-chip memory. The microcontroller can then direct the reset vector to the boot code in the on-chip memory and brings the system processor out of reset. The system processor can execute the boot code in-place on the on-chip memory, which initiates the system memory and the second stage boot loader.

Abstract: In one embodiment, the present invention includes a processor having multiple cores to independently execute instructions, a first sensor to measure a first power consumption level of the processor based at least in part on events occurring on the cores, and a hybrid logic to combine the first power consumption level and a second power consumption level. Other embodiments are described and claimed.

Abstract: An apparatus and method for reducing current consumption in a portable terminal are provided, in which upon generation of a task, a controller transitions to a Virtual Maximum Clock (VMC) level and changes a clock level from the VMC level according to a load state of the controller, to process the task. Moreover, the controller changes the clock level by at least one of transition from the VMC level to an RMC level, a stepwise increase from the VMC level, a stepwise decrease from the VMC level, and a hold at the VMC level, according to the load state of the controller.

Abstract: A step down unit steps down an external power supply voltage Vcc. A bias current control circuit controls the magnitude of bias current flowing through an auxiliary path connecting an output node and the ground. A system controller increases the magnitude of the bias current, prior to a change of the operation state of a load circuit by which a relatively large change occurs to the amount of current consumed by the load circuit including a central processing unit.