Abstract: A reprogramming device is used for reprogramming embedded systems. The reprogramming device comprises a microprocessor, a memory programmed with software to accomplish the reprogramming of distinctly different embedded systems architectures, and one or more hardware devices that facilitate communication over multiple protocols contained in a portable package designed for both one-time and multi-occurrence use scenarios. In some embodiments, the reprogramming device is able to be used to enhance one or more attributes of performance of existing embedded systems through the reconfiguration of internally stored parameters. In some embodiments, the reprogramming device is also to be used to extract and receive information and instruction from existing embedded systems and enable useful presentation of this information. As a result, the reprogramming device is able to be used to adjust and/or monitor the parameters of the on-board diagnostics computer of a vehicle to ensure peak performance and detect errors.

Abstract: A power generator adaptive to a computer apparatus is provided. The power generator includes a logic operating unit, a power converting module, and a power management module. The logic operating unit receives a power pulse signal generated by a power button when the power button is pressed. The logic operating unit generates a power enabling signal according to the power pulse signal. The power converting module receives the power enabling signal and generates an internal voltage by converting an external voltage according to the power enabling signal. The power management module receives the internal voltage and the power pulse signal, and latches a generating state of the internal voltage according to the power pulse signal to generate a power stable signal. The power management module further provides the power stable signal to the logic operating unit to maintain a generating state of the power enabling signal.

Abstract: In a secure boot method, an initial boot loader verifies a first digital signature included in a first boot loader using a public key. The first boot loader is executed if the first digital signature is valid. The first boot loader verifies a first message authentication code included in a second boot loader using a unique key. The second boot loader is executed if the first message authentication code is valid.

Abstract: A power supply assembly for a terminal having Ethernet energy supply, includes a split device with an Ethernet energy supply connection (A1) that connects to an Ethernet cable which is set up to supply energy and with an output to provide a first DC voltage (U1), a logic unit coupled to the split device, a DC/DC converter coupled to the logic unit and connected to the output of the split device in a switchable manner, and a voltage (U) that supplies the terminal being provided at an output of the DC/DC converter under control of the logic unit.

Abstract: A method for switching an operating system (OS) and an electronic apparatus are provided. While switching to a first OS, a system firmware stored in a memory unit declares that a first segment of a system memory is in a usable state and a second segment of the system memory is in a reserved state by using a first resource description table, so that the first OS is in a working state in the first segment and a second OS is in a power-saving state in the second segment. While switching to the second OS, the system firmware declares that the second segment is in the usable state and the first segment is in the reserved state by using a second resource description table, so that the second OS is in the working state and the first OS is in the power-saving state.

Abstract: The present invention may provide a system including a controller and a plurality of integrated circuits. The controller may control synchronization operations of the system, the controller may include a master timing counter and a controller data interface. Each integrated circuit may include a timing counter and an IC data interface. Further, each integrated circuit may synchronize its respective timing counter based on synchronization command received from the controller via the data interfaces. Hence, the system may provide synchronization between the controller and the integrated circuits without an extraneous designated pin(s) for a designated common time-based signal.

Abstract: Embodiments of the present invention provide a processor design that enables controller and I/O device power reduction and optimization. In a typical embodiment, a processing core is coupled to a set (e.g., three) of I/O blocks. The processing core provides for selective activation and/or deactivation of any of the I/O blocks. Two of the I/O blocks are coupled to individual voltage I/O components as well as individual external circuits. In one embodiment, the individual external circuits are coupled to individual voltage control components.

Abstract: A gateway card is connected to an information processor, and receives and transmits data between different networks. The information processor has a normal power mode and a power saving mode. A switching unit connects a memory with the information processor if the information processor is in the normal power mode, or to the gateway card if the normal power mode of the information processor is changed to the power saving mode.

Abstract: A method and apparatus to control and manage a power state in a related set of storage devices is described. In one example a method includes, determining an idleness measure at the file system, the idleness measure indicating availability requirements of the device set, and setting an idle state based on the idleness measure. The method also includes receiving the idle state setting at the storage subsystem, determining whether the idle state setting is different from a current state of the device set, determining whether to change the idle state of the device set if the idle state setting is different from the current state of the device set, the determining being based on information about the device set. The method also includes commanding the device set to change the current idle state to correspond to the idle state setting based on determining whether to change the idle state.

Abstract: An integrated circuit is disclosed that contains both a PMU and another processing portion, such as a baseband. Because of the limited pins devoted to the PMU, the PMU receives most of its signals through the other processing portion of the integrated circuit. Thus, in order to protect the PMU, the integrated circuit isolates the PMU portion from receiving different signals from the other processing portion until after certain conditions are satisfied. In addition, the integrated circuit includes a GPIO pin bank in the other processing portion that can be freely configured so as to allow for testing of the PMU.

Abstract: A method and apparatus for supporting a hibernation function in a mobile device are provided. In the method, the mobile device detects a wakeup event in a hibernation mode and, in response to the wakeup event, loads a snapshot image into a volatile memory from a snapshot image region of a nonvolatile memory. After the loading of the snapshot image, the mobile device determines whether there is a system status has been modified. If the system status has not been modified, the mobile device finishes a system boot. If the system status has been modified, the mobile device performs data synchronization and then finishes the system boot.

Abstract: The present invention provides a server including a plurality of power supplies independent from each other, a management backplane, a first embedded management board (first EMB) and a plurality of motherboards independent from each other. The power supplies are turned on or off according to a first control signal. The management backplane is coupled to the power supplies, the first EMB and the motherboards. The first EMB has a power-controlling unit and produces the first control signal and an acknowledgement signal according to the load status, the quantity of a plurality of turned on power supplies and a power-on demand command. The motherboards respectively send out the power-on demand command and decide whether or not to power on according to the acknowledgement signal, wherein when the first EMB works, a polling mode is used to sequentially switch the connections between the first EMB and the motherboards through the management backplane.

Abstract: A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.