Abstract: A ferroelectric semiconductor device (10) and a method of manufacturing the ferroelectric semiconductor device (10). The ferroelectric semiconductor device (10) has a layer (13) of ferroelectric material disposed on a semiconductor substrate (11) and a gate electrode (17) formed on a portion (26) of the layer (13) of ferroelectric material. The portion (26) of the layer (13) of ferroelectric material sandwiched between a semiconductor substrate (11) and a gate electrode (17) retains its ferroelectric activity. The portions (21, 22) of the layer (13) of ferroelectric material adjacent the portion (26) are damaged and thereby rendered ferroelectrically inactive. A source contact (31) and a drain contact (32) are formed through the damaged portions (21, 22) of the layer (13) of ferroelectric material.

Abstract: A linear CCD (charge-coupled device) including: a photodiode-array having a plurality of photodiodes for converting incident light plural charges, respectively; and a charge transfer part for transferring the charges of the photodiodes during a first phase of a first and second clock signal and for moving the charges during a second phase of the first and second clock signals. The charge transfer part includes: plural first shift electrodes connected to the photodiodes, respectively, for forming potential wells that receive charges from the photodiodes, respectively, during the first phase of the first and second clock signals; and plural second shift electrodes located between the first shift electrodes, respectively, for forming potential wells that receive the charges from the potential wells of the first shift electrodes during the second phase of the first and second clock signals. No shift gates are needed between charge outlets of the photodiodes and the first shift electrodes.

Abstract: A solid-state imaging device provided here comprises a p-type semiconductor substrate, a p-type impurity layer formed thereon, a light-intercepting part formed inside said impurity layer for storing signal charges produced through incident light, and a n-type drain part formed in a region of the substrate excluding the light-intercepting part for discharging excess charges of the light-intercepting part. As a result, sensitivity characteristics on the long wavelength side can be improved, and miniaturization can be facilitated. An n-type buried drain part for discharging charges is formed under a transfer part via a p-type impurity layer. The readout side between the light-intercepting part and the transfer part is separated by a p-type readout control part which is installed to control threshold voltage (Vt), and the non-readout side is separated by a channel stopper.

Abstract: A substrate transistor is formed, including a gate insulation region formed on a substrate, spaced apart source/drain regions formed in the substrate, and a gate electrode formed on the gate insulation region, disposed between the spaced apart source/drain regions, the gate electrode having a sidewall portion. A lateral thin film transistor is formed, including a sidewall gate insulation region on the sidewall portion of the gate electrode and a lateral channel region on the sidewall gate insulation region such that the gate electrode controls the current in the lateral channel region. A first one of the spaced apart source/drain regions of the substrate transistor preferably includes a lightly-doped inner portion disposed adjacent the gate electrode and a heavily-doped outer portion disposed adjacent the lightly-outer portion, opposite the gate electrode. The lateral channel region preferably is electrically connected to a second one of the spaced-apart source/drain regions of the substrate transistor.

Abstract: A semiconductor memory has bit lines, word lines, ground lines, and memory cells. The bit lines intersect the word and ground lines, to form intersections where the memory cells are arranged, respectively. Each of the memory cells consists of a double-emitter transistor. This transistor has a collector, a first emitter, and a second emitter. Each base-emitter junction of the transistor has an N-shaped negative differential current-voltage characteristic that shows a relatively small gain up to a peak current and a relatively large gain after a valley current. The first emitter of each transistor is connected to a corresponding one of the ground lines. The second emitter is connected to a corresponding one of the word lines. The collector is connected to a corresponding one of the bit lines. Each of the memory cells has a small number of elements and requires only a small area.

Abstract: An amplifying type solid-state imaging device having a transistor formed on a semiconductor base and a charge release portion which stores a signal charge which is generated by light incident on the transistor and outputs a change of an electrical signal in accordance with the stored charge. The transistor includes: a first gate region including a portion for storing the signal charge therein and a first gate electrode formed on the semiconductor base surface; and a source and a drain formed of impurity layers of a higher concentration than the semiconductor base concentration. The charge release portion includes: a second gate region including a portion in the vicinity of the semiconductor base surface, and a second gate electrode formed via an insulating film on the semiconductor base surface; and a drain for charge discharge formed of an impurity layer of a higher concentration than the semiconductor base concentration.

Abstract: A charge coupled device having a CCIR/EIA mode conversion function includes: a plurality of VCCD regions formed in the direction of row, the VCCD regions having a predetermined interval from one another; a plurality of HCCD regions formed at the end of the VCCD regions in the direction of column; a plurality of photodetectors regularly arranged between the VCCD regions, the photodetectors generating signal charges according to an image signal; a plurality of vertical gate electrodes formed on the VCCD regions and the photodetectors in the direction of column, the vertical gate electrodes transmitting the signal charges of the photodetectors to the HCCD regions through the VCCD regions according to applied vertical clock signals; vertical clock signal generator for supplying a predetermined number of vertical clock signals; and a selecting portion for receiving vertical clock signals from the vertical clock signal generator, the selecting portion supplying the vertical clock signals to part of the vertical gat

Abstract: A photoelectric conversion apparatus has an element separation structure that is adequate as to crosstalk between pixels and excellent in FPN characteristics. The photoelectric conversion apparatus comprises a semiconductor substrate of a first conduction type, a plurality of first semiconductor regions formed in a surface of the semiconductor substrate and having the opposite conduction type to that of the substrate, a second semiconductor region having the same conduction type as the first semiconductor regions and disposed between the plurality of first semiconductor regions thus formed, and a third semiconductor region disposed between the first and second semiconductor regions having the first conduction type, and having an impurity concentration higher than that of the semiconductor substrate.

Abstract: A field-effect transistor structure is described having a monocrystalline silicon channel region which is epitaxially continuous with an underlying monocrystalline silicon body region. Polycrystalline silicon source and drain regions abut the channel region. The source and drain regions are electrically isolated from the underlying body region by a patterned dielectric layer, which may include a thick field oxide. A polycrystalline silicon gate is capacitively coupled with the channel region by a second dielectric layer. The gate may extend laterally to partly overlap the source and drain regions.

Abstract: This invention provides TEGs for improving accuracy of lifetime evaluation. The TEGs include a base region <Ba> selectively having a cathode region <C> in the surface portion thereof, and an anode region <A>. The intersection of a center line of the cathode region <C> and the anode region <A> provides a function region <WT> located within the range of 5h, five times as much as a height h of a wafer <W>. The function region <WT> makes a pair with the cathode region <C> and actually serves as an actual anode region for the cathode region <C>. As an area ratio of the cathode region <C> to the function region <WT> is smaller, ON voltage values Vf obtained for respective lifetime values get isolated from each other. Thus, the cathode region <C> is formed so that the area ratio of the cathode region <C> to the function region <WT> is about 1/1750000 to 1/4500.

Abstract: A transistor is provided with a graded source/drain junction. At least two dielectric spacers are formed in sequence upon the gate conductor. Adjacent dielectric spacers have dissimilar etch characteristics. An ion implant follows the formation of at least two of the dielectric spacers to introduce dopants into the source/drain region of the transistor. The ion implants are placed in different positions a spaced distance from the gate conductor according to a thickness of the dielectric spacers. As the implants are introduced further from the channel, the implant dosage and energy is increased. In a second embodiment, the ion implants are performed in reverse order. The dielectric spacers pre-exist on the sidewall surfaces of the gate conductor. The spacers are sequentially removed followed by an ion implant. An etchant is used which attacks the spacer to be removed but not the spacer beneath to the one being removed.

Abstract: Described is a semiconductor photo detector comprising, between a lower electrode and an upper electrode, an optical absorption layer which generates photo carriers, receiving light and an amplification layer which amplifies the photo carriers so generated. In the semiconductor photo detector, the amplification layer is formed of a well layer which causes an avalanche phenomenon and a barrier layer which has a band gap larger than that of the optical absorption layer. The well layer is formed of a crystal substance, by which at the interface with the barrier layer, the energy value of the conduction band of the photo carriers in the well layer is lower than that in the barrier layer and at the same time, the difference in the energy value of the conduction band between the well layer and the barrier layer is larger than the band gap between the valence band and the conduction band of the well layer.

Abstract: A charge-coupled device image sensor includes a substrate, a buried channel region of a first conductivity type, formed in the substrate to a predetermined depth, for transferring signal charges, a first high concentration impurity region of a second conductivity type, formed in the substrate adjacent to the buried channel region, forming a channel stop, a first surface channel region of the second conductivity type, formed on the buried channel region, for transferring dark current charges, a second high concentration impurity region of the first conductivity type, formed on the first high concentration impurity region, for removing dark current charges from the surface channel region, and a second surface channel region of the second conductivity type formed to a predetermined depth in the substrate between the second high concentration impurity region and the first surface channel region.

Abstract: An improved solid-state image sensor is provided by having an image sensing element composed of photoelectric conversion parts, a microlens formed on the surface of the image sensing element corresponding to each photoelectric conversion part, and optical fiber bundle formed of optical fibers arranged in a two-dimensional shape and mounted on the microlens. The optical fiber bundle is also composed of a core and a clad portion. The refractive index of a filler which mounts the optical fiber bundle on the microlens is less than that of the microlens and greater than that of the clad portion of each of the optical fibers.

Abstract: A solid state image pick-up device comprises an array of a plurality of photodiodes formed on a principal surface of a semiconductor substrate, a planarizing resin layer covering the principal surface of the semiconductor substrate, and a plurality of micro lens formed on the planarizing resin layer, each of micro lens being positioned to correspond to one of the photoelectric conversion elements. The planarizing resin layer is composed of a first region of a first refractive index sandwiched between each of the micro lens and the corresponding photodiode, and a second region surrounding the first region, the second region having a second refractive index larger than the first refractive index.

Abstract: A light-emitting diode device includes a light-emitting diode, a lens cap made of synthetic resin, for covering the light-emitting surface of the light-emitting diode means, and a refractive layer formed between the light-emitting surface and the lens cap, the refractive layer having a composition, such as an air layer, with a refractive index different from the refractive index of said synthetic resin. In this arrangement the relationship between the light intensity and directional angles is shown by characteristics in which the light intensity is maximum in the center of the directional angles, and is relatively flat in the form of a sinusoid in the wide range of the directional angles. Therefore, even when the characteristics of each light-emitting diode is not verified, a predetermined light-signal transmission range is readily obtained without being affected by a scatter in the characteristics.

Abstract: The present invention utilizes a first dielectric layer and a second dielectric layer overlying cell regions for storing a turned-off state or a turned-on state, respectively. The first dielectric layer is formed by local oxidation of polysilicon having a thickness greater than that of the second dielectric layer, such that the corresponding cell regions below the first dielectric layer have a threshold voltage greater than that of the second dielectric layer. Moreover, the formation of the first dielectric layer can lower the parasitic capacitance between the word lines and the bit lines as well as the substrate. Furthermore, the present invention does not require code-implantation. Thus, decreased breakdown voltage encountered in the conventional method can be avoided.

Abstract: An asymmetrical IGFET including a lightly doped drain region, heavily doped source and drain regions, and an ultra-heavily doped source region is disclosed. Preferably, the lightly doped drain region and heavily doped source region provide channel junctions.

Abstract: When an element of an internal circuit is arranged in the vicinity of an input/output terminal of an LSI chip, electrostatic break down is caused in an internal circuit element by discharge current generated between an input/output terminal and a grounding terminal or a power source terminal. Therefore, the elements are arranged with a distance to cause dead space therebetween to make down-sizing of the LSI chip difficult. Therefore, a resistor is disposed between an input/output terminal and a protection element connected thereto. The resistor causes increasing of resistance of a current path from the input/output terminal to the grounding terminal, at the common wiring. Thus influence of the electrostatic break down for the element of the internal circuit can be restricted to permit location of the resistor to permit the internal circuit element to be arranged in the vicinity of the protection element of the input/output terminal.

Abstract: A semiconductor mask-programmable read-only-memory array structure provides double density storage of data information by means of thin film memory cell transistors formed on both sides of a layer of thin film polysilicon. At a bottom surface of a layer of thin film polysilicon which has a bottom gate oxide grown thereon, a plurality of polysilicon bottom cell wordlines intersects a plurality of bitlines to form an array of bottom cell memory transistors. The bitlines are heavily-doped diffusion regions within the layer thin film polysilicon. Additionally, a top surface of the layer of thin film polysilicon has a top gate oxide grown thereon. Over this top gate oxide, a plurality of polysilicon top cell wordlines intersects the plurality of bitlines to form an array of top cell memory transistors, thereby producing a NOR-type read-only-memory array structure with double the storage density of conventional, prior art structures.