Abstract: A semiconductor memory device conserves chip area by jointly connecting transistors which are respectively connected to pads adjacent to each other. The device includes first and second electrostatic discharge protection MOSFET transistors which have drains respectively connected to pads adjacent to each other and which define a first active area. A common source is arranged between the first and second transistors areas and defines a second active area in common to both transistors. The device is connected to a single power supply at the gates and sources thereof. The transistors also share common active ground lines.

Abstract: The invention is a storage cell capacitor and a method for forming the storage cell capacitor having a storage node electrode comprising a barrier layer interposed between a conductive plug and an oxidation resistant layer. A layer of titanium silicide is fabricated to lie between the conductive plug and the oxidation resistant layer. A thick insulative layer protects the sidewalls of the barrier layer during the deposition and anneal of a dielectric layer having a high dielectric constant. The method comprises forming the conductive plug in a thick layer of insulative material such as oxide or oxide/nitride. The conductive plug is recessed from a planarized top surface of the thick insulative layer. Titanium is deposited and a rapid thermal anneal is performed. The titanium reacts with silicide of the conductive plug to form TiSi at the bottom of the recess. Unreacted Ti is removed. The barrier layer is then formed in the recess.

Abstract: It is an object of the present invention to provide a solid-state image sensing device with a vertical shutter structure allowing the size of the solid-state image sensing device with ease. An electric-charge exhausting unit is provided on the same side of a sensor array comprising a plurality of sensor units arranged to form a straight line as an electric-charge transferring unit wherein the electric-charge exhausting unit comprising an electric-charge exhaust drain having a shape resembling an island and an electric-charge exhausting gate with a bent shape surrounding the electric-charge exhaust drain is provided in such a way that the electric-charge exhausting unit is in contact with a first region of a read gate, and only one electric-charge exhausting unit is provided for each pair of sensor units adjacent to each other.

Abstract: A DRAM semiconductor device has: a semiconductor substrate with one surface; a first well and a second well respectively formed in a first region and a second region in areas of the one surface of the semiconductor substrate, the first and second wells each having a local maximum of a first conductivity type impurity concentration at a depth position apart from the one surface of the semiconductor substrate, and one of a depth and the first conductivity type impurity concentration of the local maximum of the second well is larger than that of the first well, and the other is at least equal to that of the first well; a memory cell formed in the first well; and a peripheral circuit for the memory cell formed in the second well. A DRAM semiconductor device is provided whose refresh characteristics are improved without deteriorating other characteristics.

Abstract: A capacitor is provided for analog applications which can be fabricated with processes conventionally employed to fabricate digital circuitry and which has line spacing that is smaller than interlayer spacing. The capacitor of the present invention is based on intralayer capacitive coupling, rather than interlayer capacitive coupling which is conventionally employed in prior art capacitors. A capacitance can be achieved with the capacitor of the present invention that is higher than can be obtained with conventional capacitors occupying an area on the integrated circuit structure having similar size. Additionally, the capacitor of the present invention can be formed from upper metal layer such as metal-3, metal-4, and metal-5, and when the capacitor is formed from any of the upper metal layers the parasitic capacitance to ground is small.

Abstract: The active type solid-state imaging device of this invention having a transistor for obtaining signal charges by photoelectric conversion of incident light, accumulating the signal charges, and outputting an electric signal corresponding to the accumulated signal charges, includes an electric field strength buffering region for lowering the electric field strength between at least one of a source region and a drain region of the transistor and a photoelectric conversion region.

Abstract: A method of manufacturing a nonvolatile semiconductor memory device which is protected against deterioration in the electron injection/discharge characteristics between a floating gate of a memory cell and a channel. Three layers including a gate oxide film, a first polysilicon layer and a first nitride film are sequentially deposited on a silicon substrate surface and patterned with stripe-like columnwise lines. A second nitride film is formed on side walls of the columnwise lines, respectively. An element isolating insulation film is formed on the silicon substrate surface which is not covered with the first and second nitride films. After removal of the first and second nitride films, a first insulation film is formed on the side walls of the first polysilicon layer.

Abstract: An accumulated-base bipolar junction transistor and an application of said transistor is described. A base region of an accumulated-base bipolar junction is formed by the implantation and then the diffusion of a first dopant material into the semiconductor substrate. A base contact region is a rectangular ring of a second dopant type that is implanted and annealed into the base region. The base contact region is to form a low resistance path from the base region to external circuitry. A collector region is formed by the implantation and annealing of third dopant into the base region in the form of a rectangular ring within the base contact region and a first distance from the base contact region. An emitter region is a rectangular form implanted and annealed of the third dopant within the collector region and a second distance from the collector region.

Abstract: A capacitor in a semiconductor integrated circuit is fabricated having a fixed charge density introduced near an electrode/dielectric interface. The fixed charge density compensates for the effects of a depletion layer, which would otherwise lower the effective capacitance. By shifting the undesirable effect of the depletion capacitance outside of the operating voltage range, the capacitor is effectively converted to an accumulation mode. The fixed charge density is preferably introduced by a plasma nitridation process performed prior to formation of the capacitor dielectric.

Abstract: In a method of manufacturing a charge coupled device, a channel layer is formed on a surface of a semiconductor substrate. Then, first layer transfer electrodes are formed in a charge transfer direction above the channel layer via a first insulating film. Subsequently, second layer transfer electrodes are formed such that each of the second layer transfer electrodes is disposed between two of the first layer transfer electrodes without any portion overlapping the first layer transfer electrodes in a plane structure. The second layer transfer electrodes may be patterned after a polysilicon film is deposited and polished or may be polished after the polysilicon film is deposited and patterned.

Abstract: A structure of periodically varying density is provided, that acts as a phonon resonator for phonons capable of participating in phonon-electron interactions. Specifically, a phonon resonator that is resonant for phonons of appropriate momentum to participate in indirect radiative transitions and/or inter zone intervalley scattering events is provided. Preferably, the structure is an isotope superlattice, most preferably of silicon. The structure of the present invention has improved optical, electrical, and/or heat transfer properties. A method of preparing a the structure of the present invention is also provided.

Abstract: A charge coupled device has a plurality of N-diffused regions and a plurality of N.sup.- diffused regions arranged alternately along a charge transfer channel. A first electrode and second electrode overlying each N-diffused region and N.sup.- -diffused region form a pair of electrodes, four of which form a group of electrodes iteratively appearing along the charge transfer channel. Each first pair and each third pair are connected to a first signal line and second signal line, respectively, which receive two-phase driving clock signals, while each second pair and fourth pair are connected to a fixed potential line maintained at a middle potential between the high level and low level of the driving signals. A high-speed transfer of signal charges is obtained in the two-phase type charge coupled device.

Abstract: Semiconductor switching devices having buried gate electrodes include a substrate, a drift region of first conductivity type (e.g., N-) extending to a face of the substrate and a first insulated gate electrode buried in the drift region. The first insulated gate electrode extends laterally in the substrate in spaced relation to the face. A second gate electrode is also provided on the face at a location extending opposite the first insulated gate electrode. A base region of second conductivity type (e.g., P) is also provided in the substrate, between the second gate electrode and an upper surface of the first insulated gate electrode. Similarly, an emitter region of first conductivity type (e.g., N+) is provided between the first face and the upper surface of the first insulated gate electrode. The base region is defined so that respective P-N junctions are formed with the emitter and drift regions.

Abstract: A two-dimensional image sensor comprises a matrix array of photodiodes and multiple vertical shift registers horizontally divided into an imaging part and a memory part. During a vertical blanking period, the imaging part receives charge packets from the photodiodes and shifts the charge packets via the memory part to a matrix array of storage cells. During a subsequent horizontal blanking period, the charge packets are restored from the storage cells to the memory part and shifted downwards by the distance of a row so that the charge packets of bottom row are shifted our into a horizontal register. Remaining charge packets are then withdrawn from the memory part to the storage cells and stored therein during a subsequent horizontal scan period. During this horizontal scan period, the memory part is maintained at such a voltage that no dark currents substantially exist and the charge packets in the horizontal register are sequentially delivered to external circuitry.

Abstract: A semiconductor device including an insulating layer, a patterned conductive layer on the insulating layer, a semiconductor layer on the patterned conductive layer, and a reactive layer formed by reacting the patterned conductive layer with growth nuclei on the patterned conductive layer between the patterned conductive layer and the semiconductor layer, the growth nuclei containing any of elements in group IIIb, group IVb, group Va and group VIIb that does not constitute the conductive film and the insulating film on the surface of the conductive film.

Abstract: There is provided an imager sensor including a semiconductor substrate, a plurality of photodiode regions arranged on the semiconductor substrate in row and column directions, a plurality of charge transfer regions each disposed at a space between the photodiode regions in the row direction, the charge transfer regions transferring in the row direction signal charges generated from the photodiode regions, and an electrically conductive photoshield film covering the charge transfer regions therewith. Each of the charge transfer regions includes at least three independent transfer electrodes per a photodiode region. At least one of the three independent transfer electrodes is surrounded by the photodiode region to thereby have an isolated island shape, the rest of the transfer electrodes extend through a space between the photodiode regions in the column direction, and make electrical connection with a bus line disposed outside the semiconductor substrate.

Abstract: An input port electrostatic discharge protection circuit is disposed between the input port of an integrated circuit and an input point of an internal circuit of the integrated circuit. The input port electrostatic discharge protection circuit includes a resistor and a field device. The ends of the resistor are connected to the input port of the integrate circuit and the input point of the internal circuit, respectively, and the function of the resistor is to delay ESD pulses for preventing the input port of the internal circuit from a strike directly. The field device has double gates disposed on field oxides. The source and drain of the field device are coupled to the input port of the integrated circuit and a low-voltage source, respectively. The first gate is coupled to the drain of the field device while the second grate is coupled to the source of the field device. The field device mainly provides an ESD path.

Abstract: An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

Abstract: A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation.

Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.