Abstract: An interline sensor is constructed using photocapacitors. The vertical shift register of the interline sensor is operated in a uniphase mode, i.e., holding one of the two phase (.O slashed.2) at a D.C. potential while fluctuating the other phase (.O slashed.1) between a voltage that is sufficiently above and below that D.C. potential to facilitate transfer of charge from one phase to the next. The uniphase mode is facilitated by a single electrode that covers both the phase that is held at a constant D.C. potential and the photodetector having photocapacitor charges. The single electrode in the preferred embodiment is an indium tin oxide electrode. The charges are transferred from the photocapacitors to the vertical shift register by a third level clock into .O slashed.1 adjacent the photodetectors.It is also proposed that the same ITO electrode be utilized to for phase 2 of both the vertical and horizontal CCD shift registers.

Abstract: A method of forming an FET transistor comprises forming a stack of a gate oxide layer and a control gate electrode on a surface of a doped semiconductor substrate with counterdoped source/drain regions therein. A silicon oxide layer is formed over the stack of the gate oxide layer and the control gate electrode and exposed portions of the semiconductor substrate including the source/drain regions. Then the silicon oxide layer and the corners of the gate oxide layer are fluorinated by rapid thermal processing providing a fluorinated silicon oxide layer. The rapid thermal processing is performed in an atmosphere of NF.sub.3 gas and O.sub.2 gas at a temperature from about 900.degree. C. to about 1050.degree. C. for a time duration from about 10 seconds to about 50 seconds, and the fluorinated silicon oxide layer has a thickness from about 200 .ANG. to about 400 .ANG..

Abstract: An imaging device (10) has a plurality of unit cells that contribute to forming an image of a scene. The imaging device includes a layer of semiconductor material (16), for example silicon, that has low noise photogate charge-mode readout circuitry (20, 21, 26, 28) (e.g., CCD or CMOS readout circuitry and structures) that is disposed upon a first surface (18) of the layer. A second, opposing surface of the layer is a radiation admitting surface of the layer. The layer has a bandgap selected for absorbing electromagnetic radiation having wavelengths shorter than about one micrometer and for generating charge carriers from the absorbed radiation. The generated charge carriers are collected by the photogate charge-mode readout circuitry. A thermal sensing element (22) is disposed above and is thermally isolated from the first surface of the layer. The thermal sensing element may be, by example, one of a bolometer element, a pyroelectric element, or a thermopile element.

Abstract: A charge-coupled device comprises a substrate, a charge transfer layer on the substrate, an insulating layer on the charge transfer layer, and a sequence of electrodes divided into recurrent groups of first, second, third and fourth electrodes each, the electrodes being arranged in a single-layered structure on the insulating layer. First, second, third and fourth conductors are connected respectively to the first, second, third and fourth electrodes of each electrode group. The insulating layer permanently holds electrons in positions respectively corresponding to the second and fourth electrodes of each group. First, second, third and fourth breakdown diodes are connected respectively to the first, second, third and fourth conductors, where the first and third breakdown diodes have a first breakdown voltage and the second and fourth diodes have a second breakdown voltage higher than the first breakdown voltage.

Abstract: N.sup.+ impurity diffusion layers, and a gate electrode are formed on a major surface of a p-type semiconductor substrate. An insulating layer, and interlayer insulating layers are formed to cover gate electrode. An interconnection layer provided with a hole is formed on interlayer insulating layer. A contact hole is provided in interlayer insulating layer and a column-like portion is formed within the contact hole and hole. The column-like portion and interconnection layer constitute a bit line. Thus, the resistance of the bit line can be reduced and the manufacturing process of the device can be simplified.

Abstract: In a charge coupled device including a semiconductor substrate having a semiconductor region, a plurality of nonactive barrier electrodes, a plurality of first electrodes and a plurality of second electrodes arranged between the nonactive barrier electrodes, an outermost one of the nonactive barrier electrodes is electrically isolated from the others of the nonactive barrier electrodes.

Abstract: A novel configuration for MOS devices employed in a partially generic gate array type chip having large numbers of generally MOS devices. The MOS devices have a non-rectangular configuration and include at least a first and second region of conductivity type differing from the conductivity type of the gate array substrate that are separated by a channel over which an electrode strip such as a gate is formed. The non-rectangular configuration of the MOS devices provides a space savings that permits the presence of a greater number of devices on a single chip as compared to conventional gate array chips. In accordance with another aspect of the invention one or more patternable busses of conductive material, such as polysilicon, interconnect electrode strips of the MOS devices, such as gates strips, that are made of the same conductive material as the busses.

Abstract: A thin film transistor is described incorporating a gate electrode, a gate insulating layer, a semiconducting channel layer deposited on top of the gate insulating layer, an insulating encapsulation layer positioned on the channel layer, a source electrode, a drain electrode and a contact layer beneath each of the source and drain electrodes and in contact with at least the channel layer, all of which are situated on a plastic substrate. By enabling the use of plastics having low glass transition temperatures as substrates, the thin film transistors may be used in large area electronics such as information displays and light sensitive arrays for imaging which are flexible, lighter in weight and more impact resistant than displays fabricated on traditional glass substrates. The thin film transistors are useful in active matrix liquid crystal displays where the plastic substrates are transparent in the visible spectrum.

Abstract: A charge transfer device including a semiconductor substrate, a gate electrode provided in association with the substrate, the gate electrode having a corresponding channel region through which charge is propagated, the channel region having a predetermined potential; and means associated with the channel region for reducing charge trapping and recombination effects. In one aspect of the present invention, the reducing means includes a potential pocket defined within the channel region having a greater potential than the predetermined potential of said channel region. The potential pocket has a width dimension which is less than the corresponding width dimension of the channel region. The potential pocket is positioned in the center of the gate electrode, and is positioned so as to be aligned with a front edge of the gate electrode.

Abstract: A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M.sub.1, M.sub.2, M.sub.3 connected in parallel for respectively driving a capacitive load C.sub.L with a selected different voltage level V.sub.1, V.sub.2 or V.sub.3. Transistors M.sub.1, M.sub.2, M.sub.3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V.sub.1, V.sub.2 or V.sub.3 to charge the load CL. The largest voltage transistor M.sub.3 has its body connected to its source. The lower voltage transistors M.sub.1, M.sub.2 have their bodies respectively connected to switches S.sub.1, S.sub.2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V.sub.3 when the transistors are placed in the OFF condition.

Abstract: An integrated circuit includes an N isolation buried layer underlying high density and low voltage type P channel and N channel transistors to define islands of arbitrary voltage on the substrate. Thus such transistors, which otherwise are capable only of low voltage operation, become capable of operating at high voltage relative to the substrate. This allows integration, on a single chip, of high voltage circuit elements with low voltage and high density transistors all formed by the same fabrication process sequence. In one example this allows creation of an 18 volt range charge pump using a CMOS process which normally provides only 3 volt operating range transistors. This then allows integration on a single integrated circuit chip of a complex digital logic function such as a UART (universal asynchronous receiver and transmitter) with a high voltage function such as an RS-232 interface, including integrated capacitors for the RS-232 interface charge pump.

Abstract: An EEPROM with separated floating gate to reduce the antenna ratio is disclosed. The structure of the EEPROM includes field oxides formed on a wafer. A control gate is formed in the wafer. A first gate oxide formed above the wafer for isolation. A first polysilicon portion is formed on the first gate oxide, which includes a gate for a transistor, a first contact window and a floating gate. Further, the floating gate is set above the control gate. A second gate oxide is formed on the wafer adjacent to the field oxide for isolation. A tunneling window is formed in the second gate oxide. A second polysilicon portion having a second contact window is formed on the second gate oxide. A dielectric layer is formed on the first polysilicon portion and the second polysilicon portion. Contact holes are formed in the dielectric layer and a connecting structure formed in the contact holes and on the dielectric layer for interconnection.

Abstract: The present invention features a ROM memory cell with a non-uniform threshold voltage. The ROM memory cell includes a channel region divided into several channels deposed in parallel along the axial direction of carrier transport. Afterwards, one code-implant procedure is performed to program the memory cell to store one of multiple states, thereby constituting a multiple-state ROM, the fabrication of which does not require multiple photolithography as well as multiple implantation processes.

Abstract: Described is a semiconductor photo detector comprising, between two electrodes, at least one of said electrodes being a transparent electrode, an optical absorption layer which is composed of a non-single crystalline material, absorbs light and generates photo carriers and a carrier multiplication layer which is composed of a non-single crystalline material and multiplies the photo carriers generated by the optical absorption layer. The carrier multiplication layer is formed of a multilayer film obtained by stacking films each having plural layers which are composed of non-single crystalline Zn.sub.x Cd.sub.1-x M (0.ltoreq.x.ltoreq.1, M represents one selected from the group consisting of S, Se and Te) and are different in a composition ratio in accordance with a change in the value of x in said Zn.sub.x Cd.sub.1-x M, whereby a band discontinuity .DELTA.Ec of the conduction band can be made larger, an ionization rate of electrons can be heightened and the place where ionization occurs can be specified.

Abstract: A method of fabricating a thin film transistor by setting the temperature of a heat treatment for crystallizing an active layer which is formed on a substrate at a level not deforming the substrate and activating an impurity layer in a heat treatment method different from that employed for the heat treatment, and a semiconductor device prepared by forming a heat absorption film, a semiconductor film, a gate insulating film, and a gate electrode on a substrate, the heat absorption film being provided within a region substantially corresponding to the semiconductor film.

Abstract: A three-dimensional ROM device includes a silicon substrate having plurality of parallel trenches formed in an upper surface thereof, and a plurality of raised mesa regions. Each trench has a bottom and a pair of sidewalls, and is separated from an adjacent trench by a respective mesa region. A plurality of separated, parallel source/drain regions are provided, including a first and second source/drain region located on respective opposite sides of a respective trench bottom, and a third and fourth source/drain region located on respective opposite sides of a respective raised mesa region. Each source/drain region serves as a bit line. A gate oxide layer is located on the upper surface of the silicon substrate. A plurality of sidewall oxide layers are formed on selected sidewalls and serve as channel barriers. A plurality of silicon nitride layers are formed above selected mesa regions and trench bottoms, and serve as channel barriers.

Abstract: The present invention provides a semiconductor multi-layer structure which has a channel layer made of a first compound semiconductor having a first conduction band edge level. The channel layer has a first thickness sufficient for confining a two-dimensional electron gas. The semiconductor multi-layer structure also has a donor layer overlying the channel layer. The donor layer is made of a second compound semiconductor having a second conduction band edge level higher than the first conduction band edge level. The donor layer is doped with an impurity. The donor layer is sufficiently thin for allowing electrons to show a tunneling across the donor layer. The semiconductor multi-layer structure also has a single quantum well layer overlying the donor layer. The quantum well layer is made of a third compound semiconductor having a third conduction band edge level lower than the second-conduction band edge level.

Abstract: Very high resistance values may be necessary in integrated circuits, for example in the gigaohm range, for example for realizing RC times of 1 ms to 1 s. Such resistance values cannot or substantially not be realized by known methods in standard i.c. processes because of the too large space occupation. In addition, known embodiments are usually strongly dependent on the temperature. According to the invention, therefore, two zener diodes (10, 4; 11, 4) connected back-to-back are used as the resistor. The current through each zener diode is mainly determined by band--band tunneling when the voltage is not too high, for example up to approximately 0.2 V. This current has a value such that resistors in the giga range can be readily realized on a small surface area. Since the current is mainly determined by intrinsic material properties of silicon, the temperature dependence is very small. The resistor may furthermore be manufactured in any standard CMOS process or bipolar process.

Abstract: A method for forming a CMOS device, with improved yield, performance and reliability characteristics, has been developed. Yield improvements have been addressed by the use of a dual insulator spacer, used to reduce the risk of salicide bridging, as well as the use of pocket implantation regions, used to reduce punchthrough leakage. An ultra shallow junction extension region has been created in a peripheral channel region, reducing the resistance of this region, thus enhancing the performance of the CMOS device. In addition, ultra lightly doped source and drain regions are used to relax reliability concerns, regarding hot electron injection.

Abstract: A method of forming BiCMOS circuitry includes, i) conducting a first common second conductivity type implant into, a) a first substrate area to comprise a second conductivity type well for a first area first conductivity type FET, and b) a third substrate area to comprise one of a bipolar transistor second conductivity type collector or emitter region; ii) providing field oxide regions and active area regions within first, second and third areas of the substrate; iii) conducting a first common first conductivity type implant into, a) the second substrate area to comprise a first conductivity type channel stop region beneath field oxide in the second area, and b) the third substrate area to comprise the bipolar transistor base; and iv) conducting a second common second conductivity type implant into, a) at least one of the first or the second substrate areas to comprise at least one of a source/drain implant or a graded junction implant for at least one of the first or second conductivity type FETs, and b) the