Abstract: The invention relates to an opto-electronic sensor component comprising the following: a first semiconducting layer of predetermined conductivity type and a second layer of different semiconductor or metal conductivity type; a transition region between the two layers; at least one surface region through which the electromagnetic radiation to be detected can pass into the transition region (radiation-side surface region); and an electrode for each layer to connect both layers to an electrical circuit. The electrodes of the two layers are mounted on a surface of the component opposite a radiation-side surface region. This simplifies connection of the sensor component to an electrical circuit mounted on a circuit board or the like.

Abstract: A method for producing a back-illuminated CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. The semiconductor substrate is secured to a protective substrate by an adhesive such that the processed (frontside) surface of the semiconductor substrate faces the protective substrate. With the protective substrate providing structural support, the exposed backside surface of the semiconductor substrate is then subjected to grinding and/or chemical etching, followed by optional chemical/mechanical processing, to thin the semiconductor substrate to a range of 10 to 15 microns. A transparent substrate (e.g., glass) is then secured to the backside surface of the semiconductor substrate, thereby sandwiching the semiconductor substrate between the transparent substrate and the protective substrate.

Abstract: An electrode structure for use on an integrated circuit, and a method for forming the same. The electrode structure is formed by depositing a polysilicon layer on a dielectric layer. The polysilicon layer is then annealed until a plurality of non-contiguous polysilicon clusters are formed. Each of the non-contiguous polysilicon clusters has a base end and a top end. The base ends of the non-contiguous clusters are preferably separated by a spacing (S). Following the annealing step, the non-contiguous polysilicon clusters are connected electrically by depositing a conductive layer having a thickness (T) over the annealed polysilicon layer. The spacing (S) is preferably greater than twice the thickness (T).

Abstract: An image sensor having a plurality of pixels comprising a semiconductor material of a first conductivity type with at least two adjacent pixels, each of the pixels has a photodetector formed within the substrate and an electrical function that is shared between the adjacent pixels integrated within the adjacent pixels. The electrical function can be: a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion, a reset drain, a lateral overflow gate, an overflow drain or an amplifier, that is shared between multiple pixels resulting in a saving of space.

Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor comprises the steps of forming a first dielectric film on a substrate, forming a MIM capacitor on the first dielectric film, forming a second dielectric film covering the MIM capacitor, selectively removing the first and second dielectric films to expose the substrate surface, surface treating using a hydrochloric acid solution, forming a third dielectric film on the second dielectric film and the substrate, and forming a transistor on the third dielectric film. The second dielectric film protects the capacitor insulator film of the MIM capacitor.

Abstract: The NMOS transistor is provided with a semiconducting substrate (12) which is p-doped and comprises a top side (14), and with a first region (16) which is n-doped and placed into the substrate by diffusion from the top side (14) of the substrate (12). Further, the transistor comprises a second region (18) arranged within the n-conducting region (16), which is n-doped and introduced into the substrate from the top side (14) of the substrate (12), and a field oxide layer (20) which is arranged on the top side (14) of the substrate (12) and limits the p-conducting region (16) on all sides. The top side comprises a source region (22) and a drain region (24) which are n-doped and arranged within the p-conducting region (18) at a distance to each other. A gate oxide layer (26) is arranged on the top side (14) of the substrate (12) between the source and the drain regions (22, 24).

Abstract: An I/O protection circuit includes a P-channel MOS transistor connected between an input terminal and a power supply line, and an N-channel MOS transistor connected between the input terminal and a ground line. Gate electrodes of both the transistors are floated. The transistors may be replaced with gate diodes. Further, gate electrodes may be formed from the same layer as a gate electrode provided for field shielding.

Abstract: A solid state image pick-up device is disclosed in which potential wells formed between adjacent ones of charge transfer electrodes of a vertical charge transfer portion thereof, formed between adjacent ones of charge transfer electrodes of a horizontal charge transfer portion and formed in a connecting region between the vertical and horizontal charge transfer portions are uniformalized. Impurity densities of regions between the charge transfer electrodes of the vertical charge transfer portion thereof, between the charge transfer electrodes of the horizontal charge transfer portion and in a connecting region between the vertical and horizontal charge transfer portions are set independently from each other on the basis of the inter-electrode distances and amplitudes and potentials of driving pulses supplied these electrodes such that these potential wells become equal to each other.

Abstract: The invention is directed to reducing incidental capacitance associated with a MOS transistor, especially such a transistor as used with a solid-state image-pickup device, without reducing the channel conductance of the MOS transistor. To such end, N.sup.+ -type high-concentration fields are formed near the surface of a P-type well field that in a semiconductor substrate. An N-type low-concentration field is formed between and surrounding the N.sup.+ -type high-concentration fields. A depletion layer is formed by making PN junctions between N.sup.+ -type high-concentration fields and the well field in a reverse-bias state to deplete the perimeter of the N.sup.+ -type high-concentration fields and the entire N-type low-concentration field.

Abstract: A solid-state image sensor and a fabricating method thereof in which poly gates in a horizontal charge coupled device (hereinafter referred to as HCCD) are made to have different lengths to omit a barrier ion implanting process step, thus simplifying the entire process and maximizing the charge-transferring efficiency are disclosed, the solid-state image sensor having an HCCD and VCCDs including a well region of a second conductivity type formed in a semiconductor substrate of a first conductivity type; a HCCD of the first conductivity type formed on the well region of the second conductivity type; and a plurality of polygate electrodes having sequentially different lengths repeatedly formed on the semiconductor substrate.

Abstract: An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

Abstract: A semiconductor device including a substrate (220) having a primary surface, a memory cell (202) provided on the substrate, the memory cell (202) including a P-channel transistor, the P-channel transistor having an N-type gate (72), and peripheral portion (204) provided on the substrate, the peripheral portion including a P-channel transistor , the P-channel transistor having a P-type gate (99). A method for forming the semiconductor device is also disclosed.

Abstract: In a charge transfer device of the two-layer electrode, two-phase drive type, an N.sup.-- semiconductor region 108 and a first insulator film 103 are formed on a P-type semiconductor substrate 101 in the named order. Then, first transfer electrodes 104A are formed on the first insulator film 103, and a second insulator film 105 is formed on the surface of the N.sup.-- semiconductor region 108 and a third insulator film 105 is formed on a top surface and a side surface of each first transfer electrode 104A. Phosphorus is ion-implanted with an incident angle of 0 degree, so that an N-type semiconductor region 102A is formed in N.sup.-- semiconductor region 108 between the first transfer electrodes 104A in self-alignment. Second transfer electrodes 109A are formed, and an interlayer insulator 110 is formed on the whole, and metal interconnections 111-1A and 111-2A are formed.

Abstract: A CCD image device in which the potential variation of a charge transferring region caused by a CST layer is minimized to enhance the charge transfer efficiency, is disclosed including a plurality of photo-detectors arranged regularly in row and column directions in the surface of a substrate of a first conductivity type; a plurality of charge transferring regions of a second conductivity type formed between the photo-detectors of the row direction; and a channel stop layer formed in the surface of the substrate in order to electrically insulate the respective photo-detectors and the respective charge transferring regions from each other. A CST doping concentration reducing region for decreasing the doping concentration of the channel stop layer is formed at least one in each part to which the neighboring two photo-detectors are adjacent.

Abstract: A solid-state photographic element that can perform electronic shutter action simultaneously for all pixels is disclosed. Each pixel includes a photoelectric converter (such as a photodiode), a first transfer gate, a charge storage element, a second transfer gate, an amplifier, and a reset element. All photodiodes are first reset, then the first transfer gates selected OFF at the same time and charges accumulate in all photodiodes simultaneously. After a predetermined shutter time has elapsed, the first transfer gates are selected ON at the same time and charges that accumulated in the photodiodes are transferred to the corresponding charge storage elements. Thereafter, first transfer gates are selected OFF. A vertical scanning circuit may then select second transfer gates ON sequentially for each row, so that charges accumulated in the charge storage elements are transferred to control regions of corresponding amplifiers.

Abstract: In an LDD structure MOSFET, a protecting multilayer insulating film is formed to cover a gate electrode in order to protect the gate electrode and the gate oxide film from a moisture included in an upper level layer. The protecting multilayer insulating film includes a protecting nitride film for preventing infiltration of moisture, and another protecting insulator film having a compressive stress for relaxing a tensile stress of the protecting nitride film. Thus, it is possible to prevent infiltration of moisture, and simultaneously, it is possible to minimize energy levels for trapping electrons and holes, which would have otherwise been formed within the gate oxide film and at a boundary between the gate oxide film and the semiconductor substrate because of the tensile stress of the protecting nitride film.

Abstract: On a p.sup.++ substrate (1) provided is a p.sup.- epitaxial layer (2) having an impurity concentration lower than that of the p.sup.++ substrate (1). A p well (3) is formed in a portion of the p.sup.- epitaxial layer 2 and further n.sup.+ diffusion layers (4a and 4b) are selectively formed in the p well (3). A memory cell capacitor (5) is connected onto the n.sup.+ diffusion layer 4b. On the other hand, an no diffusion layer (6) is selectively formed in the p.sup.- epitaxial layer (2) separately from the p well (3), to which an external signal input circuit (7) is connected. Further, a p.sup.++ diffusion layer 9a is provided between the external signal input circuit (7) serving as a source for injection of the minority carriers, i.e., electrons and the n.sup.+ diffusion layer (4b) connected to the memory cell capacitor (5), for blocking the entry of the minority carries. The p.sup.++ diffusion layer (9a) extends up to such a depth as to reach the p.sup.++ substrate (1) from a surface of the p.sup.

Abstract: In each of basic cells (BC) arranged in array in an SOI layer, PMOS and NMOS transistors are symmetrically formed. Body regions (11) and (12) are formed to divide source/drain layers (1) and (2), respectively, and gate electrodes (3) and (4) are formed on the body regions (11) and (12) respectively to sandwich gate insulating films therebetween. The gate electrodes (3) and (4) are connected at their both ends to gate contact regions (5) to (8), respectively, and the body regions (11) and (12) are connected at their one ends to body contact regions (9) and (10), respectively. The body contact regions (9) and (10) are so arranged as to sandwich the gate contact regions (5) and (7) together with the gate electrodes (3) and (4), respectively. Being of a SOI type, the device achieves high-speed operation and low power consumption.

Abstract: An integrated circuit device in which the gate oxide of the devices in the integrated circuit device is selected to control plasma damage during device processing is disclosed. The integrated circuit device has at least two transistors, each transistor having a source, drain, gate and channel. At least one device has a channel length that is greater than 0.5 .mu.m and at least one device has a channel length that is less than 0.5 .mu.m. The device having a channel length that is greater than 0.5 .mu.m has a gate oxide thickness that is less than the gate oxide thickness of the device having a channel length that is less than 0.5 .mu.m. The relative thickness of the gate oxide for the shorter channel devices and the longer channel devices is selected so that the tunneling leakage current that passes through the gate oxide for the longer channel devices is at least two orders of magnitude greater than the tunneling current through the gate oxide of the shorter channel devices.

Abstract: A field effect transistor and a method for forming the field effect transistor are made up of a source region which is formed on the substrate, a drain region which is formed on the substrate, a stepped portion which is formed in the substrate between the source region and the drain region, a gate insulating film which is formed on the stepped portion of the substrate, and a gate electrode which is formed on the gate insulating film, wherein, a thickness of the gate insulating film near the drain region, which is less than that of the gate insulating film on a channel region defined in the substrate between the source region and the drain region. Accordingly, the field effect transistor and a method for forming the field effect transistor can prevent degradation of transistor characteristics because of a hot carrier effect.