Abstract: By using conventional spacer and etch techniques, microstructure elements, such as lines and contact openings of integrated circuits, may be formed with dimensions that are mainly determined by the layer thickness of the spacer layer. In a sacrificial layer, an opening is formed by means of standard lithography and etch techniques and, subsequently, a spacer layer is conformally deposited, wherein a thickness of the spacer layer at the sidewalls of the opening substantially determines the effective width of the microstructure element to be formed. By using standard 193 nm lithography and etch processes, gate electrodes of 50 nm and beyond can be obtained without significant changes in standard process recipes.

Abstract: A substrate whose elemental constituents are selected from Groups III and V of the Periodic Table, is provided with pre-defined masked regions. Etching of the substrate comprising the steps of: a) forming a gas containing molecules having at least one methyl group (CH3) linked to nitrogen into a plasma; and b) etching the unmasked regions of the substrate by means of the plasma. For a substrate whose elemental constituents are selected from Groups II and VI of the Periodic Table, the plasma etching gas used is trimethylamine. Since the methyl compound of nitrogen has a lower bond energy than for hydrocarbon mixtures, free methyl radicals are easier to obtain and the gas is more efficient as a methyl source. In addition, compared with hydrocarbon mixtures, reduced polymer formation can be expected due to preferential formation of methyl radicals over polymer-generating hydrocarbon radicals because of the lower bond energy for the former.

Abstract: A method for etching trenches having different depths on a semiconductor substrate includes providing a mask with first and second openings. The first and second openings are located where corresponding first and second trenches are to be etched. A slow-etch region, made of a slow-etch material, is provided above the substrate at a location corresponding to the second opening. When exposed to a selected etchant, the slow-etch material is etched at a rate less than the rate at which the semiconductor substrate is etched when exposed to the selected etchant.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.

Abstract: A method is used to form a circuit to achieve a high-speed performance and a circuit to attain a high reliability on one and the same substrate, in a semiconductor integrated circuit device containing MIS transistors, in which the gate insulating film is made of a high dielectric constant insulating film. In the method, the high dielectric constant insulating film is removed on the diffusion regions of the MIS transistors in the logic region and I/O region, and silicide layers of a low resistance are formed on the surfaces of the diffusion regions. In the memory region, on the other hand, the silicide layers are not formed on the diffusion regions of the MIS transistors, and the diffusion regions are covered with the high dielectric constant insulating film, thereby preventing damage to the semiconductor substrate during forming of the spacers, silicide layers, and contact holes.

Abstract: There is provided a method of performing a surface treatment, such as coating, denaturation, modification and etching, on a surface of a substrate. The method comprises the steps of bringing a surface treatment gas into contact with a surface of a substrate, and irradiating the surface of the substrate with a fast particle beam to enhance an activity of the surface and/or the surface treatment gas, thereby facilitating a reaction between the surface and the gas. The fast particle beam may be selected from a group consisting of an electron beam, a charged particle beam, an atomic beam and molecular beam. For example, during a coating operation, chemical deposition of predetermined component elements of the gas onto the surface is effected and a predetermined portion of the surface of the substrate is irradiated with a particle beam to form a coating layer on the predetermined portion.

Abstract: A method for preparing a semiconductor wafer for whole wafer backside inspection is disclosed. The frontside of the wafer is covered with a protective frontside substrate and the backside portion of the wafer is thinned using conventional techniques. The whole wafer backside is then polished and a backside substrate, preferably of transparent material is juxtaposed to the backside of the wafer, such as with an adhesive or with a frame. The frontside substrate is then removed, exposing electronic devices for device inspection. The backside of the wafer is maintained open or available to backside inspection such as emission microscopy techniques used to detect defects which emit light.

Abstract: A CMP oxide slurry includes an aqueous solution containing abrasive particles and two or more different passivation agents. Preferably, the aqueous solution is made up of deionized water, and the abrasive particles are a metal oxide selected from the group consisting of ceria, silica, alumina, titania, zirconia and germania. Also, a first passivation agent may be an anionic, cationic or nonionic surfactant, and a second passivation agent may be a phthalic acid and its salts. In one example, the first passivation agent is poly-vinyl sulfonic acid, and the second passivation agent is potassium hydrogen phthalate. The slurry exhibits a high oxide to silicon nitride removal selectivity.

Abstract: A method for manufacturing a magnetic random access memory is disclosed. An interlayer insulating film is formed on a lower read layer, a cell region of the interlayer insulating film is etched according to a photo etching process using a cell mask, and a MTJ layer is formed on the lower read layer of the cell region and the interlayer insulating film of a peripheral circuit region. The sidewall of the interlayer insulating film is exposed, the MTJ layer is left merely in the cell region by lifting off the interlayer insulating film, and a bit line which is an upper read layer connected to the MTJ layer is formed in a succeeding process. Accordingly, an effective area of an MTJ cell is obtained and the properties and reliability of the MRAM are improved.

Abstract: Under the first embodiment of the invention, back-end etching is applied to the specimen that needs to be inspected. Its surface is cleaned and mounted on a glass surface with the surface of the poly gate silicide that needs to be inspected being in contact with the surface of the glass. The exposed surface of the sample that is to be examined contains silicon, this silicon is removed. The gate oxide is then removed followed by the removal of the remaining poly of the gate structure. The second embodiment of the invention addresses poly gate inspection by enhanced (top surface of the gate electrode) gas etching of the gate electrode to remove gate oxide and silicon remains from the environment of the silicide. The specimen is etched back to the contact layer using a conventional Chemical Mechanical Polishing (CMP) process. The polished surface of the specimen is next exposed to XeF2, which selectively removes the oxide while the silicide remains in place.

Abstract: A substrate processing method comprises providing a substrate 105 comprising etch resistant material 210 in a process zone 155, such as an energized gas zone in a process chamber 110. The etch resistant material 210 may comprise a resist material 230 over mask material 240. The process may further comprise removing the etch resistant material 210, such as the resist material 230, in the process zone 155 before etching underlying layers.

Abstract: A method of etching a substrate includes placing a substrate in a process zone. The substrate has a material with a thickness, and the material has exposed regions between features of a patterned mask. An etchant gas is introduced into the process zone. The etchant gas is energized to etch the material. An endpoint of etching the material of the substrate is determined by (i) reflecting a light beam from the substrate, the light beam having a wavelength selected to have a coherence length in the substrate of from about 1.5 to about 4 times the thickness of the material, and (ii) detecting the reflected light beam to determine an endpoint of the substrate etching process. Additionally, the wavelength of the light beam can be selected to maximize an absorption differential that is a difference between the absorption of the light beam in the patterned mask and the absorption of the light beam in the material.

Abstract: An aqueous dispersion is used in the chemical mechanical polishing of surfaces, particularly oxidic surfaces, such as silicon dioxide. The aqueous dispersion contains a powder of pyrogenically produced silicon dioxide doped with 0.01 and 3 wt. % aluminium oxide, relative to the total amount of powder, said powder having an average particle diameter in the dispersion of not more than 0.1 ?m.

Abstract: A method of forming contact holes. A dielectric liner is comformally formed on a substrate, parts of the dielectric liner between the second and the third conducting structure are removed, a conductive liner is conformally formed on the substrate, and parts of the metal layer are removed to leave parts thereof between the second and the third conducting structure. An ILD layer is then formed on the entire surface of the substrate, and a patterned photoresist layer is formed on the ILD layer. Finally, the ILD layer is etched using the patterned photoresist layer as a mask to form a first contact hole, a second contact hole, and a third contact hole in the ILD layer at the same time.

Abstract: The present invention provides a method of polishing a semiconductor device comprising, polishing the semiconductor device with a polishing pad, the polishing pad comprising, a polymeric matrix and a dissolvable substance. The dissolvable substance is located at a work surface of the polishing pad and in a subsurface proximate the work surface. The method further comprises dissolving the dissolvable substance at the work surface while polishing the semiconductor device and wearing away the polishing pad while polishing the semiconductor device such that the subsurface becomes a new work surface that polishes the semiconductor device.

Abstract: The present invention is directed to methods for editing copper features embedded within an organic body by exposing at least a portion of a top surface of the copper feature, forming a mill box there-over and then simultaneously milling both the copper feature and any organic material exposed through the mill box in a single step using an ion beam in combination with a XeF2 gas for a dwell time of at least 10 milliseconds. The invention dramatically increases the efficiency of Focused Ion Beam milling of copper features embedded in organic layers by milling these features in a gas-depleted environment at significantly increased dwell time while avoiding the problems of graphitization, destruction of the organic layer and metal redeposition.

Abstract: A method for forming an opening in an organic insulating layer by covering the insulating layer with a bilayer containing a resist hard mask layer and a resist layer on top of the resist hard mask layer. The bilayer is patterned, and an opening is created by plasma etching the insulating layer in a reaction chamber containing a gas mixture. The plasma etching is controlled so that virtually no etch residues are deposited and so that the side walls of the opening are fluorinated to enhance the anisotropy of the etching. The gas mixture can be a mixture of a fluorine-containing gas and an inert gas, a mixture of an oxygen-containing gas and an inert gas, or a mixture of hydrogen bromide and an additive.

Abstract: A method and apparatus for monitoring a process by employing principal component analysis are provided. Correlated attributes are measured for the process to be monitored (the production process). Principal component analysis then is performed on the measured correlated attributes so as to generate at least one production principal component; and the at least one production principal component is compared to a principal component associated with a calibration process (a calibration principal component). The calibration principal component is obtained by measuring correlated attributes of a calibration process, and by performing principal component analysis on the measured correlated attributes so as to generate at least one principal component. A principal component having a feature indicative of at least one of a desired process state, process event and chamber state then is identified and is designated as the calibration principal component.

Abstract: Disclosed is a method for fabricating a semiconductor device having at least one contact holes formed by employing a self-aligned contact (SAC) etching process. The contact holes are formed through the shortened number of sequential steps by using different process recipes. First, an anti-reflective coating (ARC) layer formed on a substrate structure prepared sequentially with a substrate, conductive structures, an etch stop layer and an inter-layer insulation layer is etched by employing an etch gas of CF4, O2, CO and Ar. Then, a portion of an inter-layer insulation layer is etched with use of an etch gas of CF4 and O2. The rest portion of the inter-layer insulation layer is subsequently etched by using a different etch gas of C4F6, CH2F2, O2 and Ar to thereby form at least one contact hole exposing the etch stop layer.

Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.