Abstract: Oxygen induced lattice slip defects are reduced in device layer 26 of silicon-on-insulator structure 12, 16, 26. At the bottom of trenches 22 notches 28 are etched into the dielectric layer 16. A thermal oxide process provides protrusions 30 of oxide into the substrate. The protrusions 30 direct defects into the support layer 12.

Abstract: Methods of forming electrically isolated active regions in semiconductor substrates include the steps of forming a plurality of trenches in a face of a semiconductor substrate to define an active region pedestal between first and second dummy region pedestals and then forming an electrically insulating layer on the active region and dummy region pedestals and in the trenches disposed therebetween. A mask is then patterned to expose a portion of the electrically insulating layer on the active region pedestal and then the exposed portion of the electrically insulating layer is etched so that a thickness of the electrically insulating layer on the active region pedestal is less than a thickness of the electrically insulating layer on the first and second dummy region pedestals. A step is then performed to planarize the electrically insulating layer to selectively expose the active region pedestal but not the first and second dummy region pedestals.

Abstract: A process for forming a shallow trench isolation is disclosed. Initially, a gate oxide layer is formed on a substrate, and a silicon nitride, which defines an active area, is then patterned on the gate oxide layer. Next, hemispherical grain silicon is formed on the silicon nitride, the sidewalls of the silicon nitride, and the exposed gate oxide layer. Portions of the gate oxide layer are removed to form oxide islands using the silicon nitride and the hemispherical grain silicon as mask. Thereafter, portions of the substrate are removed using the oxide islands as mask. Finally, the exposed substrate is thermally oxidized to form the field oxide structure of the present invention.

Abstract: Novel silica particulates adopted for formulation into dentifrice compositions have a unique surface chemistry as to be at least 50% compatible with zinc values, and have a number of OH functions, expressed as OH/nm.sup.2, of at most 15 and a zero charge point (PZC) of from 3 to 6.5.

Abstract: A semiconductor structure to prevent gate wrap-around and corner parasitic leakage comprising a semiconductor substrate having a planar surface. A trench is located in the substrate, the trench having a sidewall. An intersection of the trench and the surface forms a corner. A dielectric lines the sidewall of the trench. And, a corner dielectric co-aligned with the corner extends a subminimum dimension distance over the substrate from the corner.

Abstract: Field oxide regions are formed in a dry oxygen environment containing controlled amounts of HCl at elevated temperatures to reduce edge defects of narrow source/drain regions.

Abstract: Planarization of geometrically difficult semiconductor device surfaces is accomplished utilizing a coating technique in which on an object with a flat surface is used to planarize the coating material. In particular, device processing is accomplished by including a step that produces a planar surface by coating a nonplanar surface with a material that has a viscosity of less than 1000 cp. An object with a flat surface is placed into contact with the material in such a manner that the material is planarized to a desired degree. The material is cured while in contact with the object's flat surface. The object is then separated from the material. The planarity of the planarizing material is then transferred into the underlying layer using conventional techniques.

Abstract: A method for producing an isolation region on a surface of a semiconductor substrate includes: forming and patterning a masking layer; forming an isolating layer so that a notch exists between an edge of the masking layer and the upper surface of the isolating layer; forming a filling layer over the masking layer and the isolating layer, so that it completely fills the notch; forming field protection spacers adjacent to the masking layer; partially removing the filling layer to expose the upper surface of the isolation layer, the notch remaining filled with a part of the filling layer; and selectively etching the isolating layer from its upper limit until this upper limit is substantially coplanar with the upper surface of the semiconductor substrate. A transistor may be produced in a semiconductor substrate, having a minimum gate length, a minimum width isolation region and wide field isolation region.

Abstract: The aim of the present invention is to obtain a thin-film transistor which has a small OFF current. A film whose main component is aluminum and which will be the gate electrode is formed in an island shape, and a porous oxide layer is formed on its side surfaces by an anodic oxidation process. A source region and a drain region are then formed by performing impurity ion implantation. Further, the aforementioned oxide layer is removed, and lightly doped regions are formed by once again performing impurity ion implantation. In this way it is possible to obtain a construction which has lightly doped regions between the source/drain regions and the channel-forming regions.

Abstract: Planarized field isolation regions are formed in a semiconductor substrate to isolate adjacent semiconductor devices by implanting an isolation material, such as oxygen or nitrogen ions, into a substrate patterned to define the field isolation regions. The implanted isolation material combines with the silicon in the substrate to form a field isolation region that extends downward from the surface of the substrate.

Abstract: A process for forming a narrow field oxide layer with a greater thickness. A silicon substrate is provided on which a layer of pad oxide and a layer of nitride are formed. Then, at least a wide area and a narrow area are defined on the silicon substrate through openings on the nitride layer. A thermal oxidation process is performed so as to grow a first oxide layer on the wide area and a second oxide layer on the narrow area. A polysilicon layer is then deposited over the entire surface. After that, chemical-mechanical polish (CMP) is applied so as to rub away part of the polysilicon layer that is lying above a plane coincident with the topmost surface of the nitride layer, thereby leaving a first polysilicon layer on the first oxide layer and a second polysilicon layer on the second oxide layer. A thermal oxidation process is performed so as to oxidize the first polysilicon layer and the second polysilicon layer, thereby increasing the thickness of the first oxide layer and the second oxide layer.

Abstract: Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.

Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of one of either nitrogen or fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features.

Abstract: A new method of local oxidation using an oxynitrided pad oxide layer to suppress the growth of a bird's beak is described. An oxide layer is provided over the surface of a semiconductor substrate. The oxide layer is annealed in a nitrogen atmosphere whereby the oxide layer is nitrided. The nitrided oxide layer is then reoxidized. A silicon nitride layer is deposited overlying the oxide layer. Portions of the silicon nitride and oxide layers not covered by a mask pattern are etched through to provide an opening exposing the portion of the semiconductor substrate that will form the field oxidation. The silicon substrate within the opening is oxidized wherein the semiconductor substrate is transformed to silicon dioxide wherein the nitrided oxide layer suppresses the formation of the bird's beak whereby the field oxidation is formed with a small bird's beak. The remaining oxide and silicon nitride layers are removed completing the field oxidation of the integrated circuit.

Abstract: An improved method of gap filling shallow trench isolation with ozone-TEOS is described. A pad oxide layer is provided over the surface of a semiconductor substrate. A nitride layer is deposited overlying the pad oxide layer. A plurality of isolation trenches is etched through the nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. A plasma enhanced SiH.sub.4 oxide layer is deposited over the nitride layer and over the thermal oxide layer within the isolation trenches and treated with N.sub.2 plasma. Thereafter, an ozone-TEOS layer is deposited overlying the plasma enhanced SiH.sub.4 oxide layer and filling the isolation trenches. The ozone-TEOS layer and the plasma enhanced SiH.sub.4 oxide layer are polished away stopping at the nitride layer. This completes the formation of shallow trench isolation in the fabrication of the integrated circuit device.

Abstract: A method for the fabrication of semicondictor devices is disclosed, having a field oxide isolation which is co-planar with the adjacent silicon surface and which introduces lower mechanical stresses in the adjacent silicon than prior methods which seek co-planarity by removal of silicon by anisotropic etching methods. Instead, the excess silicon is removed by oxidation followed by selective oxide removal. A silicon substrate is provided and a multilayer oxidation mask is formed on it's surface consisting of a thin thermal oxide and a thicker film of silicon nitride. the mask is patterned by standard photolithographic methods and the field oxide region is pieced by selective reactive-ion-etching. The silicon is not penetrated in this step as it is in prior art. Instead a layer of silicon oxide it thermally grown to a thickness dependent upon the final field oxide thickness. This oxide is then unidirectionally etched to the silicon interface, leaving side pockets.

Abstract: A method for isolating the elements of semiconductor devices, in which bird's beak can be restrained by accumulating nitrogen atoms between a pad oxide film and a silicon substrate and the etch depth of a silicon substrate can be controlled by use of wet etch to remove the oxide which is grown on the silicon substrate at a low temperature after formation of nitride spacer, thereby reproducing good profiles of the field oxide film.

Abstract: A method for forming a semiconductor device that can reduces the in size or height of a step generated near the mouth of a trench as compared with steps formed according to conventional methods. A semiconductor substrate is selectively removed to produce a trench therein. Next, the trench is filled with polysilicon. A top end of the polysilicon is lower than a surface of the substrate and a hollow space is produced at the top end of the trench. Then, a silicon filler is selectively formed on the top end of the polysilicon in the trench by crystal growth. A top end of the filler is substantially on the same level with the surface of the substrate. The top end of the filler is preferably higher than the surface of the substrate by -0.1 .mu.m to +0.2 .mu.m.

Abstract: A semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes providing a semiconductor substrate having field and active area regions; forming masking material over the active area region and leaving the field region exposed, the masking material comprising first, second and third layers, and having a sidewall; exposing the semiconductor substrate to first oxidation conditions effective to form field isolation oxide of a first thickness over the exposed field region; forming an etch stop material layer over the sidewall; removing at least a portion of the third layer selectively relative to the etch stop material layer; and subjecting the semiconductor substrate to second oxidation conditions effective to grow the field isolation oxide to a second thickness on the exposed field region of the semiconductor substrate.

Abstract: An EEPROM device in which a high voltage is applied to the chip during the memory cell operation and a method for the manufacturing the same are disclosed. On a P-type semiconductor substrate, a first N-well is formed in a surface portion of the substrate in the cell array region and a second N-well is formed in a first surface of the substrate in the peripheral circuit region. An EEPROM memory cell is formed on the first P-well and a first NMOS transistor is formed on the second P-well. Also, a second NMOS transistor is formed on a second surface portion of the semiconductor substrate in the peripheral circuit 10 region and a PMOS transistor is formed on the second N-well. The impurity concentrations of the first and second P-wells are controlled in accordance with the characteristic of the MOS transistors to be formed. Further, a second NMOS transistor having a resistance against a high voltage is directly formed on the P-type substrate. Thus, the electric characteristic of the EEPROM device is enhanced.