Abstract: A method is provided wherein a gate dielectric film that is plasma nitrided in a chamber of one system is subsequently heated or “annealed” in another chamber of the same system. Processing delay can be controlled so that all wafers processed in the system experience similar nitrogen content.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A capacitor (100) is disclosed that is formed as part of an integrated circuit (IC) fabrication process. The capacitor (100) has conductive top and bottom electrodes (140, 144) and a nonconductive capacitor dielectric (142). In one example, the dielectric (142) includes first and second thin dielectric layers (112, 114) that sandwich a layer of antireflective material (118). The thin layers (112, 114) provide the dielectric behavior necessary for the capacitor while the antireflective layer (118) promotes reduced feature sizes by mitigating reflected standing waves, among other things.

Abstract: A field effect transistor includes a first semiconductor region forming a channel region, a gate electrode insulatively disposed above the first semiconductor region, source and drain electrodes formed to sandwich the first semiconductor region in a channel lengthwise direction, and second semiconductor regions formed between the first semiconductor region and the source and drain electrodes and having impurity concentration higher than the first semiconductor region. The thickness of the second semiconductor region in the channel lengthwise direction is set to a value equal to or less than depletion layer width determined by the impurity concentration so that the second semiconductor region is depleted in a no-voltage application state.

Abstract: A field-effect transistor has a channel region in a bulk semiconductor substrate, a first source/drain region on a first side of the channel region, a second source/drain region on a second side of the channel region, and an extension of epitaxial monocrystalline material formed on the bulk semiconductor substrate so as to extend away from each side of the channel region.

Abstract: A light emitting device includes: (a) a light emitting layer including an electroluminescent organic material dispersed in a matrix, wherein the matrix contains a non-electroluminescent organic polymer having a Tg of at least 170° C., and each of the organic polymer and the electroluminescent organic material constitutes at least 20 percent by weight of the light emitting layer; and (b) electrodes in electrical communication with the light emitting layer and configured to conduct an electric charge through the light emitting layer such that the light emitting layer emits light. A method for manufacturing a flexible organic light emitting device, includes providing the light emitting layer and providing electrodes above and below the light emitting layer, wherein the electrodes are in electrical communication with the light emitting layer.

Abstract: Methods and apparatus utilizing a stepped floating gate structure to facilitate reduced spacing between adjacent cells without significantly impacting parasitic capacitance. The stepped structure results in a reduced surface area of a first floating gate in close proximity to an adjacent floating gate with substantially no reduction in coupling area, thus facilitating a reduction in parasitic capacitance leading to improved gate coupling characteristics. Also, because of the reduced surface area exposed to adjacent floating gates, the floating gates may be formed with reduced spacing, thus further leading to improved gate coupling characteristics.

Abstract: A semiconductor device and a fabricating method for the same are disclosed, in which when forming a capacitor sacrificial film pattern, even if a misalignment occurs, the degradation of the dielectric property due to a direct contact between the contact plug and the dielectric medium can be prevented. The semiconductor device includes a connecting part connected through an insulating layer of a substrate to a conductive layer, a seed separating layer formed around the connecting part and the insulating layer to provide an open region exposing at least part of the connecting part, a seed layer filled into the open region of the seed separating layer and a capacitor. The capacitor includes of a lower electrode formed upon the seed layer, a dielectric medium formed upon the lower electrode, and an upper electrode formed upon the dielectric medium.

Abstract: A substrate for a pre-soldering material and a fabrication method of the substrate are proposed. The substrate having at least one surface formed with a plurality of conductive pads is provided. An insulating layer is formed over the surface of the substrate in such a way that a top surface of each of the conductive pads is exposed. Next, a conductive film and a resist layer are formed in sequence on the insulating layer and the conductive pads, wherein a plurality of openings are formed in the resist layer to expose a part of the conductive film above the conductive pad. Then, a pre-soldering material is deposited over the conductive pad by stencil printing or electroplating process.

Abstract: A method for reducing dendrite formation in a self-aligned, silicide process for a semiconductor device includes forming a silicide metal layer over a semiconductor substrate, the semiconductor device having one or more diffusion regions, one or more isolation areas and one or more gate structures formed thereon. The concentration of metal rich portions of the metal layer is reduced through the introduction of silicon thereto, and the semiconductor device is annealed.

Abstract: Disclosed are a contact plug in a semiconductor device and method of forming the same. After a junction region where a contact plug is formed upwardly up to the bottom of a metal wire, the raised junction region and the metal wire are connected by a contact plug. Or after a first contact plug of the same area is formed on the junction region up to the bottom of the metal wires, the first contact plug is connected by a second contact plug. Thus, the width of the contact plug except for some portions is increased by maximum. It is thus possible to prevent an electric field from being concentrated and prohibit on-current from reduced, thus improving the electrical properties of devices.

Abstract: A conductive line Structure. In one embodiment of the invention, a conductive line includes at least two outer conductive portions, an inner conductive portion between the outer conductive portions, separated from the outer conductive portions by at least two trenches along the conductive line, and at least one connecting portion disposed in each trench connecting the inner conductive portion and the outer conductive portions.

Abstract: The present invention provides a method of planarizing a substrate, the method including, forming, on the substrate, a patterned layer having a first shape associated therewith; and processing the patterned layer, with the first shape compensating for variations in the processing such that upon processing the patterned layer, the patterned layer comprises a substantially planar shape.

Abstract: A method for fabricating a shallow trench isolation (STI) structure is described. A patterned mask layer is formed on a substrate. An ion implantation is performed to form a doped region in a predetermined depth in the substrate exposed by the mask layer. An etching process is conducted to etch the substrate down to the doped region to form a shallow trench. Thereafter, an isolating material is filled into the shallow trench to form an STI layer. The doped region is located directly under the STI layer, and no doped region is formed in the sidewall of the shallow trench.

Abstract: A semiconductor device includes semiconductor substrate, a trench capacitor formed in the semiconductor substrate, a cell transistor formed so as to the trench capacitor and having a gate electrode formed on the semiconductor substrate and a source/drain region formed in a surface of the semiconductor substrate, an impurity diffusion region formed in the semiconductor substrate so as to be electrically connected between the trench capacitor and the source/drain region, and a Ge inclusion region formed between the impurity diffusion region and the trench capacitor.

Abstract: A method of providing a freestanding semiconductor layer on a conventional SOI or bulk-substrate silicon device includes forming an amorphous or polycrystalline mandrel on a monocrystalline base structure. A conformal polycrystalline semiconductor layer is then formed on the mandrel and on the base structure, wherein the polycrystalline layer contacts the base structure. The polycrystalline semiconductor layer is then recrystallized so that it has a crystallinity substantially similar to that of the base structure. Thus, a freestanding semiconductor layer is formed with a high degree of control of the thickness and height thereof and maintaining a uniformity of thickness.

Abstract: An integrated circuit device is fabricated upon a semi-conductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Abstract: A process for nitriding materials containing silicon to form a silicon nitride material predominantly in the alpha phase is disclosed which includes nitriding the silicon-containing material by (a) heating the silicon-containing material in an atmosphere containing at least hydrogen in the temperature range of about 0.degree. C. to about 800.degree. C. and (b) thereafter, nitriding the silicon-containing material by subjecting the silicon-containing material to a nitriding atmosphere containing at least nitrogen gas in the temperature range of from about 1000.degree. C. to about 1450.degree. C. to effect nitriding.

Abstract: A first silicon single crystal substrate and a second silicon single crystal substrate are bonded together and the first silicon single crystal substrate is formed thin as an SOI layer. An insulation film is buried in portions of the bonding surface of one of the two silicon single crystal substrates, and in addition, a polycrystal silicon layer is formed on the bonding surface of the silicon single crystal substrate on the side into which the insulation film is buried.

Abstract: A method for forming an isolation region in an integrated circuit is disclosed. The method includes forming a pad layer (12) on a semiconductor substrate (10), and forming an oxidation masking layer (14) on the pad layer, wherein the pad layer relives stress from the oxidation masking layer. Next, the oxidation masking layer and the pad layer are patterned and etched to expose a portion of the substrate. After laterally removing the pad layer to form at least one undercut under the oxidation masking layer, a doped layer (16) is conformably formed on the oxidation masking layer, the pad layer, and the substrate, thereby refilling the undercut with the doped layer. Finally, the doped layer is anisotropically etched to form spacers (16A) on sidewalls of the oxidation masking layer and the pad layer, and the substrate is then thermally oxidized to form the isolation region (18) in the substrate, wherein doping atoms in the doped layer will diffuse into the substrate.