Abstract: A process for producing liquid fuels from heavy hydrocarbons such as residual oil in which the cracking temperatures are in the range of 800.degree. F. to 1200.degree. F., and the residence times are between 0.05 seconds and 0.50 seconds.

Abstract: A method of manufacturing a semiconductor device, in which trenches (7) are formed in a surface (2) of a silicon body (1), which trenches are filled with silicon oxide (11). The filled trenches are used as field-oxide regions (12) in integrated circuits. The silicon oxide is deposited from a gas phase and is subsequently densified by means of a thermal treatment in an NO or N.sub.2 O-containing atmosphere. The deposited silicon oxide can be densified in a very short period of time, and, in addition, the thermal treatment does not cause crystal defects. The method can suitably be used for "single wafer processing".

Abstract: A trench for isolating active devices on a semiconductor substrate, formed by creating a trench which has a peripheral edge, and disposing an isolating material in the trench. The isolating material extends over the peripheral edge of the trench, thereby covering at least a portion of the substrate surrounding the trench, and substantially limiting leakage of the active devices disposed on the substrate.

Abstract: An apparatus in accordance with this invention includes an alignment mark that is formed in a substrate. The alignment mark extends across a dice line so that, upon dicing the substrate, the mark is exposed in the substrate's side edge. The mark is formed at a predetermined distance from a position at which a feature is desired to be formed on the substrate's side edge using a mask. Accordingly, the mark is a positional reference that can be used for highly accurate placement of the feature on the side surface of the substrate with the mask. Preferably, the mark is formed of metal or other material enhanced to a size that is readily detectable by an alignment system with which the mark is to be used. The invention also includes methods for making the alignment mark.

Abstract: A heterojunction bipolar transistor based on the InP/InGaAs materials family and its method of making. An n-type collector layer, principally composed of InP is epitaxially grown on an insulating InP substrate by vapor phase epitaxy. The collector layer is then laterally defined into a stack, and semi-insulating InP is regrown around the sides of the stack to the extent that it planarizes with the stack top. The semi-insulating InP electrically isolates the collector stack. A thin base layer of p-type InGaAs, preferably lattice matched to InP, is grown over the collector stack, and an n-type emitter layer is grown over the base layer. A series of photolithographic steps then defines a small emitter stack and a base that extends outside of the area of the emitter and collector stacks. The reduced size of the interface between the base and the collector produces a lower base-collector capacitance and hence higher speed of operation for the transistor.

Abstract: A process for making thin gate oxides comprising the layering of a semiconductor substrate with at least an oxide layer and a nitride layer. The layers are then patterned and etched, thereby exposing portions of the substrate. The substrate is then doped, thereby creating a channel stop region. The exposed portions of the substrate are oxidized, thereby creating a field oxide region. The oxide and nitride layers are removed, thereby exposing sites of active areas, and a gate oxide layer grown in an ozone-containing atmosphere.

Abstract: A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures.

Abstract: Methods of forming trench isolation regions include the steps of forming trenches in a semiconductor substrate using an etching mask having openings therein, and then patterning the mask to enlarge the openings. The trenches and the enlarged openings are then filled with an electrically insulating material and then the insulating material is planarized using a polishing technique (e.g., CMP) and/or a chemical etching technique, to define the final trench isolation regions. Here, at least a portion of the etching mask is also used as a planarization stop. Using these methods, trench isolation regions can be formed having reduced susceptibility to edge defects because the periphery of the trench at the face of the substrate is covered by the electrically insulating material.

Abstract: A method for forming an element isolating film of a semiconductor device, which is capable of achieving a reduction in topology and a reduction in the occurrence of a bird's beak phenomenon, so that subsequent processes can be easily carried out to fabricate highly integrated semiconductor devices.

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract: A method for isolating a first active region from a second active region, both of which are configured within a semiconductor substrate. The method comprises forming a trench in the semiconductor substrate between said first active region and said second active region. A first dielectric layer is then formed on said trench and a polysilicon layer is deposited on said first dielectric layer. The polysilicon layer is then thermally oxidized to form a second dielectric layer. Preferably the first dielectric is a thermal oxide 40 to 500 angstroms in thickness consuming less than 200 angstroms of said first active region and said second active region. The polysilicon layer is preferably between 1000 to 2000 angstroms.

Abstract: A method for forming a semiconductor sensor device comprises providing a substrate (4) and forming a sacrificial layer (18) over the substrate. The sacrificial layer (18) is then patterned and etched to leave a portion (19) on the substrate (4). A first isolation layer (6) is formed over the substrate (4) and portion (19) of the sacrificial layer and a conductive layer (12), which provides a heater for the sensor device, is formed over the first isolation layer (6). The portion (19) of the sacrificial layer is then selectively etched to form a cavity (10) between the first isolation layer (6) and the substrate (4), the cavity (10) providing thermal isolation between the heater and the substrate.

Abstract: A semiconductor fabrication method for forming an insulation film and a first anti-oxidation film sequentially on a substrate which is sectioned into each of a peri region and a cell region. An active pattern is formed in the cell region and a first field ion-implanted region in a first conductive well of the cell region. Side wall spacers are formed on each side wall of the active pattern in the cell region. An active pattern is formed in the peri region by selectively etching the first anti-oxidation film and the insulation film so as to expose a certain surface portion of the peri region substrate therethrough. A first field ion-implanting region is formed in a first conductive well of the peri region by ion-implanting highly concentrated first conductive impurities through the exposed substrate and a second field ion-implanted region in a second conductive well of the peri region.

Abstract: A composite body includes a semiconductor substrate having an oxide layer formed thereon and a nitride layer formed over the oxide layer. First and second deep trench configurations are formed in the composite body. To form a shallow isolation trench between the first and second deep trench configurations, intrinsic polysilicon upper layers of the first and second deep trench configurations and the nitride layer are planarized. A titanium layer is formed over the planarized composite body and caused to react with the intrinsic polysilicon upper layers to form first and second titanium silicide caps over the first and second deep trench configurations. A masking layer is formed over the composite body such that an opening exposes the region between the first and second deep trench configurations. An etching step that is selective to titanium silicide is then performed with the first and second deep trench caps serving as masks.

Abstract: Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

Abstract: A method for filling a trench within a substrate. There is first provided a substrate having a trench formed within the substrate. There is then formed over the substrate and within the trench a silicon layer. The silicon layer has an aperture formed therein where the silicon layer is formed within the trench. There is then formed upon the silicon layer and filling the aperture a gap filling silicon oxide trench fill layer. The gap filling silicon oxide trench fill layer is formed through an ozone assisted sub-atmospheric pressure chemical vapor deposition (SACVD) method. Finally, the substrate is annealed thermally in an oxygen containing atmosphere to form within the trench an oxidized silicon layer from the silicon layer, where the oxidized silicon layer is contiguous with a densified gap filling silicon oxide trench fill layer simultaneously formed from the gap filling silicon oxide trench fill layer.

Abstract: Visible light LEDs are produced having a layer of conjugated polymer which is cast directly from solution or formed as a gel-processed admixture with a carrier polymer. The LEDs can be formed so as to emit polarized light.

Abstract: A silicon substrate has patterned thereon a pad oxide layer and a nitride layer. The exposed surface of the silicon substrate is cleaned of residual oxide, and a layer of oxidizable material such as polysilicon is deposit over the resulting structure. The polysilicon layer is anisotropically etched to form spacers on the side of the nitride layer portions, which are also in contact with the silicon substrate, the etching continuing into the silicon substrate. Field oxidation is then undertaken, with the polysilicon spacers being oxidized, as is a portion of the silicon substrate, the spacers causing initial oxidation during field oxide growth to be removed from the sides of the nitride layer portions, so that encroachment of the oxide under the nitride layer portions is avoided.

Abstract: In the wafer-bonding method of fabricating an SOI (silicon-on-insulator) substrate, even if there exists thickness variation in the silicon layer, devices fabricated onto the silicon layer, in accordance with the present invention, have a decreased threshold voltage variation. According to the present invention, after bonding two wafers, the thickness of the thinned silicon layer atop the SOI substrate is measured to precisely determine the local thickness distribution. However, the fabricated devices' threshold voltage depends upon the doping concentration as well as the thickness of the silicon layer. Shielding masks of photoresist are thereafter formed selectively on a portion of the silicon that are thicker. Then, through the masks as shielding, impurities are implanted into the silicon layer to adjust the doping concentration therein. Accordingly, the doping concentration is varied corresponding to the thickness, with the result that the threshold voltage variation nearly approaches zero.

Abstract: A device isolation trench is formed in a semiconductor substrate by forming spaced apart masking regions on the substrate, leaving an exposed portion of the substrate disposed therebetween. A masking layer is formed on the masking regions and the exposed portion of the substrate. The masking layer and the substrate are then anisotropically etched for an etching time sufficient to remove the masking layer and portions of the substrate disposed between the masking regions and thereby form a device isolation trench in the substrate having rounded edges. Preferably, the step of anisotropically etching includes etching with an etchant that etches the substrate and the masking layer at approximately the same etching rate. More preferably, the substrate is silicon and the masking layer is polysilicon or amorphous silicon. The masking layer may also be high-thermal oxide (HTO) having an etching rate lower than that of the substrate.