Abstract: A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.

Abstract: The present invention is a method of making an integrated circuit device including a pair of MOSFETs each of which has a source or drain region which shares a common active region with the other. The method includes forming an epitaxial layer from nucleation sites, one of which is the source or drain region of the first MOSFET. The second MOSFET is then formed in the epitaxial layer so that one of the source or drain regions extends from one of the nucleation sites.

Abstract: An annealing method for activating ion-implanted layers of a compound semiconductor substrate which comprises a step of converting gas containing prescribed components into plasma through an electron cyclotron resonance process and making the same read with a reactive gas to deposit reaction products onto the surface of the compound semiconductor substrate having the ion-implanted layers thereby forming a protective film; and a step of performing heat treatment for activating the ion-implanted layers. The gas converted into plasma through the electron cyclotron resonance process is N.sub.2, O.sub.2, NH.sub.3 or a gas mixture thereof, preferably NH.sub.3.

Abstract: A process for manufacturing semiconductor devices according to the present invention comprises a step for thermally oxidizing semiconductor substrates (1), (12), to form first and second oxide films (24), (25) on one main surface and on another main surface thereof, respectively; a step for selectively implanting impurity inons via said first oxide film (24) to form elements in said semiconductor substrates (1), (12); a step for successively forming a film (30) that constitutes a source of impurity diffusion and a protective film (31) on said second oxide film (25); and a step of common heat-treatment for forming predetermined diffused layers (17), (18) on said one main surface of said semiconductor substrates (1), (12) by diffusing at least one kind of the impurity ions that are implanted, and for forming a diffused layer on said another main surface of the semiconductor substrates (1), (12) by diffusing impurities contained in the film (30) that constitutes said source of impurity diffusion into said semico

Abstract: In the present invention, asperity in the floating gate of an EPROM or EEPROM device is reduced. An improved process for fabricating ultrahigh coupling interpoly isolation dielectrics comprising a structure of oxide-nitride-oxide is disclosed. The first oxide is grown on undoped LPCVD polycrystalline silicon (polysilicon) to reduce the grain boundary-oxidation enhancement effect at the interface of floating gate polysilicon and interpoly oxide. This results in much higher breakdown capability of interpoly dielectrics. As a consequence, the shrinkage of the interpoly electrical thickness to an extent far beyond current limitation becomes possible. Implanted dopants through interpoly oxide into the floating gate polysilicon also eliminate the oxidation enhanced diffusion from conventional POCl.sub.3 doped polysilicon into tunnel oxide. The phosphorus induced trap in the tunnel oxide region are reduced. The EEPROM threshold window can remain open beyond 10.sup.6 cycles.

Abstract: A method for forming a submicron width metal line on a substrate is described incorporating the steps of coating a substrate with a layer of photoresist, baking the layer, exposing the layer to a pattern, soaking the layer in a solution including chlorobenzene, developing the layer to form openings, baking the photoresist to remove any residual chlorobenzene, exposing the layer to deep ultraviolet radiation, baking the layer to cause the layer to flow at the edges of the openings, depositing metal on the layer and on the substrate, and dissolving the layer to lift off the metal disposited on the layer whereby the metal deposited on the substrate remains. The invention overcomes the problem of forming submicron width metal lines from one micron openings in a photoresist layer.

Abstract: A DMOS power transistor has a vertical gate and a planar top surface. A vertical gate fills a rectangular groove lined with a dielectric material which extends downward so that source and body regions lie on each side of the dielectric groove. Carriers flow vertically between source and body regions and the structure has a flat surface for all masking steps.

Abstract: A semiconductor device is set forth comprising a number of parallel first electrodes (1) which are located on an insulating layer and are mutually separated by grooves with insulated walls, in which second electrodes (2) coplanar with the first electrodes (1) are provided. According to the invention, the first electrodes (1) are covered by an insulating layer provided with first contact windows (7), which each overlap at least one second electrode (2). The second electrodes (2) are provided with self-aligned second contact windows (8). Each second electrode (2) exhibits between its second contact window (8) and the first contact windows (7) overlapping the second electrode and also between said first contact windows (7), at least one interruption (9).

Abstract: A new CMOS device which avoids latchup while achieving a spacing between the n-channel and p-channel FETs of the device smaller than 10 .mu.m, as well as a method for fabricating the choice, is disclosed.The inventive device, which is formed in a substrate comprising a relatively heavily doped bulk region supporting a relatively thin, moderately doped layer, includes a polysilicon-filled trench extending through a portion of the layer, between the n- and p-channel FETs of the device. The inventive device also includes a relatively heavily doped region extending from a bottom of the trench to the bulk region. The polysilicon-filled trench, in combination with both the relatively heavily doped region and bulk region, prevents latchup.

Abstract: A method for making a semiconductor device, such as a power-MOS transistor, wherein dopant is introduced into the structure underlying a lead contact pad to create a conducting subregion which minimizes electrical conductive breakdown.

Abstract: A method for fabricating an integrated circuit including at least one metal-oxide-semiconductor transistor (MOS) and at least one bipolar transistor is disclosed. The pocket regions used to reduce the short channel effect in the MOS transistor are formed simultaneously with the base region for the bipolar transistor.

Abstract: An integrated circuit in complementary circuit technology comprising two field effect transistors (T1, T2) of different channel types with the first one (T2) mounted in a doped semiconductor body (1) having a first conductivity type and the other FET (T1) mounted in a semiconductor zone 2 of a second conductivity type which is arranged in said body. The object is to provide a protection against thermal overloads which can appear due to "latch up" influences when overvoltages at the one connecting region of the field effect transistor (T1) mounted in the semiconductor zone occur.

Abstract: A subsurface zener diode is formed in an N type semiconductor substrate such as the kind employed in the epitaxial layer found in silicon monolithic PN junction isolated integrated circuits. A P+ anode is ion implanted into and diffused from an oxide source and an N++ cathode is diffused within the confines of the anode. The cathode is surrounded with a counter-doped region that forces the PN junction breakdown subsurface. The resulting diode has a clean, sharp breakdown curve and the breakdown voltage can be tailored by controlling the anode deposition.

Abstract: In a method of manufacturing a solar cell including a p-n junction formed in a semiconductor substrate, impurity ions are implanted through a mask in the form of an oxide film covering a light receiving surface of the semiconductor substrate except an electrode forming part, thereby forming a p-n junction which is deep in an area beneath the electrode forming part but shallow in the remaining area. Formation of the shallow p-n junction improves the spectral sensitivity in a short wavelength range. Further, utilization of the oxide film as a passivation film can prevent shortening of the life time of minority carriers in the substrate due to heat treatment, thereby retarding the electron-hole recombination rate at the light receiving surface of the substrate.

Abstract: A method of making a vertical field effect transistor (FET) having a plurality of gates which are isolated from each other. Each gate has a contact thereby enabling a single gate which is turned "on" to cause the vertical FET to conduct a current. This configuration allows for a logical "or" function to be implemented in a vertical FET.

Abstract: A method for the manufacture of a pn-junction having high dielectric strength starting with a doped semiconductor body of a first conductivity type. A zone of a second conductivity type is formed in the semiconductor body inwardly from a surface thereof. At least one recess is then provided inwardly from the surface and including a recess which is formed at the extreme marginal edge of the semiconductor body. Dopant of the second conductivity type is diffused into the semiconductor body to form zones of varying dopant penetration depths from the center of the body to the marginal edge.

Abstract: A GTO switch is provided in which the upper base layer (gate) is formed by a diffusion step. An epitaxial layer grown over the upper base layer contains cathode and gate diffusions which are separated by an undiffused gap. This "buried base" technique provides precise control over the resistivity of the base. The cathode-gate gap provides increased reverse gate voltage capacity. Other features include a large anode short area and a double-layer-metal; contact structure on the cathode-gate surface.

Abstract: Two insulating layers may be employed to define boundaries of junctions in transistor structures useful in integrated circuit fabrication. The junctions may overlie one another, have approximately equal areas, and terminate in the insulating layers.

Abstract: A silicon-on-insulator (SOI) device is fabricated by forming at least one island of semiconductor material on a surface of an insulating material. Silicon is then formed on the areas which surround the at least one island. The silicon is oxidized to form silicon dioxide regions which surround the at least one island.

Abstract: A structure and method for use in optical communication systems is provided in which a metal is diffused in a heterojunction region beneath a metal contact of a AlGaAs light emitting diode. This structure and method significantly reduces the contacting shadowing problem due to current crowding beneath the contact thus increasing the light output from the device.