Abstract: A method of manufacturing a MOS semiconductor device which comprises a first step of forming a p-type well region in the surface of an n-type silicon substrate, a second step of forming a field oxide layer surrounding part of the surface of the well region, a third step of ion-implanting a n-type impurity into the surface of the well region, to reduce the carrier density of the well region in the vicinity of the ion-implanted without changing the conductivity type of the well region, a fourth step of forming a gate electrode insulatively on the ion-implanted surface of the well region, and a fifth step of forming the n.sup.+ -type source and drain regions in the ion-implanted surface of the well region. The third step of this manufacturing method uses the field oxide layer for implanting the n-type impurity, as a mask.

Abstract: A process for the production of a MIS-type integrated circuit is disclosed.

Abstract: A process for the fabrication of "low temperature"-gate MESFET structures, i.e., gate metal deposition takes place after annealing of an n.sup.+ -implant that form source- and drain- contact regions. The process permits self-alignment of all three important MESFET parts, namely, the implanted contact regions, and both, the ohmic, as well as the gate, contact metallizations. In the process, a multi-layer "inverted-T" structure is used as a mask for the n.sup.+ -implant and for the ohmic and gate metallizations. The upper part of the "inverted-T" is a so-called dummy gate which is replaced by the Schottky gate after ohmic contact metal deposition. The source-gate and drain-gate separations are determined by the shoulders of the lower layer of the "inverted-T", the shoulders being obtained using sidewall techniques.

Abstract: An integrated circuit structure comprises a plurality of islands of semiconductor material (16-1 through 16-5) each island being separated from adjacent islands by a groove formed in annular shape around said island to laterally define the dimensions of each such island, an oxide (12, 14) formed over the surface of said grooves (13-1 through 13-6) and said islands and a selected glass (15) deposited on said oxide (14) in the grooves and over the top surface of said device, said glass having the property that it flows at a temperature beneath the temperature at which dopants in the islands of semiconductor material substantially redistribute, said selected glass (15) having a substantially flat top surface thereby to give said structure a substantially flat top surface.

Abstract: Method of diffusing sulfur into gallium arsenide without degrading the surface of the gallium arsenide. A gallium arsenide wafer is placed in close proximity to a quantity of powdered gallium sulfide intermixed with powdered gallium arsenide. The assemblage is heated in an open-tube furnace in the presence of flowing nitrogen to vaporize sulfur while the gallium arsenide and gallium sulfide are in thermodynamic equilibrium whereby sulfur diffuses into the gallium arsenide wafer without eroding the surface.

Abstract: A green color light emitting ZnSe diode having a pn junction is fabricated by the use of a ZnSe crystal having a good crystal perfection and being obtained by a solution growth method relying on the temperature difference technique using a solvent containing at least Te and Se and using atoms of at least one kind of impurity selected from Group Ib elements of the Periodic Table as a principal impurity for producing a p type region in the crystal.

Abstract: A method of manufacturing a semiconductor device, in which a layer (12) comprising silica and an oxide of a dopant is provided on a surface (9) of a silicon semiconductor body (1). The semiconductor body is then subjected to a heat treatment at a temperature at which transport of the dopant takes place from its oxide to the seminconductor body. The heat treatment is carried out at a first stage in an atmosphere comprising an inert gas to which up to 25% by volume of oxygen is added, at a second stage in an atmosphere of practically dry oxygen and then at a third stage in an atmosphere comprising oxygen and hydrogen. Thus, a doped zone is formed in the semiconductor body, while the surface is covered with an insulating layer of high quality.

Abstract: A method of manufacturing a semiconductor device having an integrated circuit in an epitaxial layer on a substrate in which the epitaxial layer comprises islands of conductivity type opposite to that of the substrate which are surrounded laterally by a surrounding region of the same conductivity type as the substrate, is disclosed. Both the islands and the surrounding region are formed by diffusion from buried layers through the epitaxial layer. A bipolar transistor is provided in at least one island. The p-n junctions between the islands and the surrounding region are substantially at right angles to the surface. The invention involves a method of manufacturing the device and is of particular importance for realizing very compact and fast circuits with low dissipation consisting of a combination of CMOS bipolar subcircuits.

Abstract: This method, requiring a smaller number of masking steps with respect to the known methods, comprises boron implant on the surface of an epitaxial layer, without masking, and arsenic implant in predetermined locations of the epitaxial layer surface by means of an appropriate mask. A subsequent thermal treatment then leads to diffusion of the implanted arsenic and boron atoms, but boron diffusion in the regions in which arsenic implant has also occurred is prevented by the interaction with the latter, to thereby obtain regions with an N.sup.+ type conductivity where both boron and arsenic have been implanted and regions of P type conductivity where only boron has been implanted.

Abstract: For the p-type doping of silicon, particularly for power semiconductor components, aluminum from an Al target is precipitated by cathode sputtering in an argon plasma on a major face (2) of a silicon wafer (1) by which means a comparatively high purity of the deposited aluminum is achieved. Before the aluminum deposition, the silicon water (1) is bombarded with argon ions for 10 min at an argon pressure of 20 .mu.bar which guarantees a uniform fusion of the aluminum with the silicon during later heating and, in particular, prevents the formation of droplets of the aluminum on the major face (2). The Al layer formed in this manner is photo-lithographically preferably structured in such a manner that several aluminum sources spaced apart from each other are allocated to one aluminum-doped zone (10). The subsequent diffusion occurs for 300 min at 1250.degree. C. in a gas mixture of nitrogen or argon (1 l/min) and oxygen (20 ml/min). During this process, the aluminum-doped zone (10) is produced.

Abstract: Process and structure for semiconductor chip capacitors having high capacitance with variations in applied voltage without adding process steps to fabricate same.

Abstract: A liquid phase epitaxy method for the manufacture of silicon layers containing semiconductor structures involving the epitaxial deposition of silicon using a melt of a metal as the solvent, the metal forming silicon saturated solutions below 900.degree. C., and not producing any doping in the layers corresponding to a concentration greater than 10.sup.17 doping atoms/cm.sup.3. A gold melt is preferred because the melting point of the gold-silicon eutectic is about 370.degree. C. The invention provides for implementing the liquid phase epitaxy at very low temperatures and, thus, producing single crystal silicon layers on substrates provided with insulation layers, and required for the manufacture of three-dimensional integrated circuits in microelectronics.

Abstract: An eight mask process for forming a lateral insulated gate semiconductor device is disclosed. The gate structure can be used as a mask to align the third and fifth regions of the device and a third protective layer aligns the fourth and sixth regions of the device.

Abstract: Vertical PNP and the NPN transistors, each having a gain-bandwidth product greater than 1 GHz are formed in dielectrically isolated regions in polysilicon substrate. The substrate may include additionally dielectrically isolated regions for other devices such as thin oxide capacitors. On one surface of the substrate between the respective device regions a thick field insulator (oxide) layer is formed to minimize parasitics between interconnects and the substrate. Atop this thick field oxide one or more thin film resistors may be formed. Contacts and interconnect metallization for the bipolar devices, capacitors and thin film resistors are preferably made of silicon-doped-aluminum. In the course of manufacture of the PNP and NPN devices like conductivity type regions are formed simultaneously so as to control the parameters of each device. The relatively high f.sub.

Abstract: A simplified process is used to obtain pattern delineation for a buried layer by making use of the metastable state of silicon to grow oxide at different rates on the surface of the silicon. A silicon substrate having dopants implanted in a predetermined location is annealed at a low temperature. Oxide is then grown on the surface of the substrate at a temperature which maintains the silicon in a metastable state. The oxide will grow faster over the doped region than it will over the undoped region thereby providing a step which can be used for pattern delineation. After the oxide is grown the substrate is diffused in order to drive the impurity to the desired depth.

Abstract: A method for the production of semiconductor devices, using liquid phase epitaxy of semiconductors of Groups III to V of the periodic table, in which on a Te-doped first layer, a second layer having a polarity different from that of the first layer is grown, wherein a non-Te-doped third layer having the same polarity as the first layer is grown between the first layer and the second layer. Another method in which on a Te-doped first layer, a second layer having a principal crystal composition different from that of the first layer is grown, wherein a non-Te-doped third layer having the same principal crystal composition of the first layer is grown between the first layer and the second layer.

Abstract: A compound semiconductor laser comprises a semi-insulating substrate, a lower clad layer, an MQW active layer, an upper clad layer, and two electrodes on the top surface thereof. The upper clad layer is formed so as to have a property of reducing the diffusion coefficient of impurities, from the lower portion toward the upper portion thereof. Impurity atoms are thermally diffused into the lower clad layer from the top surface thereof to form an N-type region and a P-type region, respectively. The side diffusion fronts of the N- and P-type regions are nearly vertical, and thus a narrow MQW active region is defined by disordered portions of the MQW active layer in the N- and P-type regions. The light and carriers are effectively confined in the narrow active region by using the vertical and transverse double-heterostructures and refractive index differences.

Abstract: A process for forming MOS transistors in which the source and drain regions essentially interface only the channel portion of the silicon substrate to keep parasitic capacitances low. To this end, a monocrystalline silicon substrate has one major planar surface covered with a layer of silicon oxide and a hole formed in the oxide layer of a size suited for the channel of the transistor. Then silicon is epitaxially grown vertically to fill the hole. The grown silicon is then covered. Next, portions of the oxide layer are removed to expose a pair of opposed vertical sidewalls of the vertically grown silicon and silicon is epitaxially grown laterally out of said exposed sidewalls. Such laterally grown regions serve as the source and drain of the transistor and an upper portion of the vertically grown silicon serves as the channel. A gate oxide is grown over a top portion of the vertically grown silicon and a polysilicon gate region is formed over the gate oxide.

Abstract: An MOS transistor having relatively low parasitic capacitances is achieved by forming a dielectrically isolated mesa on a monocrystalline substrate. Such mesa includes a polycrystalline silicon region that serves as a gate region and an oxide layer that serves as a gate oxide. Subsequently, such mesa is made to sit on a platform, arising from the silicon substrate and surrounded by a sea of silicon dioxide originally at the level of the bottom of the mesa. The level of this sea is lowered to expose opposed sides of the platform to which is grown separate regions of lateral epitaxial silicon that serve as the source and drain of the transistor.

Abstract: High phosphorus polyphosphides, namely MP.sub.x, where M is an alkali metal (Li, Na, K, Rb, and Cs) or metals mimicking the bonding behavior of an alkali metal, and where x=7 to 15 or very much greater than 15 (new forms of phosphorus) are useful semiconductors in their crystalline, polycrystalline and amorphous forms (boules and films). MP.sub.15 appears to have the best properties and KP.sub.15 is the easier to synthesize. P may include other pnictides as well as other trivalent atomic species. Resistance lowering may be accomplished by doping with Ni, Fe, Cr, and other metals having occupied d or f outer electronic levels; or by incorporation of As and other pnictides. Rectifying Schottky junction devices doped with Ni and employing Ni as a back contact comprise Cu, Al, Mg, Ni, Au, Ag, and Ti as junction forming top contacts. Photovoltaic, photoresistive, and photoluminescent devices are also disclosed. All semiconductor applications appear feasible.