Abstract: A process for forming a planarized, low sheet resistance FET. A gate stack is defined on an exposed surface of a semiconductor substrate, the gate stack including a gate mask disposed on a patterned polysilicon layer. First and second diffusion having first and second silicide electrodes are then formed on the substrate, to provide low sheet resistance source and drain electrodes. An insulating layer is then formed on the substrate, and is planarized to expose an upper surface of the gate mask. The gate mask is then removed in wet H.sub.3 PO.sub.4 to define an aperture in the insulating layer that exposes the polysilicon layer, and a conductive material is selectively grown on the substrate to provide a metal-strapped polysilicon gate electrode that is relatively co-planar with the planarized insulating layer.

Abstract: A charge coupled device (CCD) sensitive to infrared radiation composed of a succession of three layers of Group III-V semiconductor material. The layers are a window layer, a sensitive layer and a storage layer. The layers are fixed to a supporting plate serving as input for the radiation and as a rear surface of the device. The front surface of the device supports a plurality of control electrodes and at least one output electrode.The window layer and the storage layer of the CCD are made of a binary compound AB. The sensitive layer is made of an n-ary compound (A,X,Y . . . ).sub.III (B,M,N . . . ).sub.V having a larger forbidden energy band and a smaller absorption limit wavelength than the window and storage layers.The three layers of the device are formed by epitaxial growth on a substrate. The substrate is a layer of the binary compound AB coated with an epitaxial layer of the n-ary compound. The epitaxial substrate layer is a chemical blocking layer.

Abstract: A lateral p-i-n photodetector and a method of forming a lateral p-i-n photodetector in which p- and n-type regions are formed on a semi-insulator or i-type body by allowing metal and p-dopant compounds and metal and n-dopant compounds onto the i-type body. During alloying, p- and n-type regions are formed in the i-type body by diffusion of the dopants from the compounds, leaving the metallic compounds as n- and p-type contacts over respective p- and n-regions. In preferred embodiments, the i-material is either Fe doped InP or InGaAs.

Abstract: A heterojunction bipolar transistor having excellent high-frequency characteristics is manufactured by forming a semi-insulating semiconductor layer on a collector (or emitter) layer, removing a part of the semi-insulating semiconductor layer to form a cut portion so that the collector layer is exposed at the cut portion, growing a base layer on the semi-insulating semiconductor layer, on a slant wall of the cut portion and on the exposed part of the collector layer, and growing an emitter (or collector) layer on the base layer. A base layer may be preliminarily formed on the semi-insulating semiconductor layer before forming the cut portion. Energy band gap of the emitter is greater than that of the base.

Abstract: A layer of HgCdTe (15) is epitaxially grown on a crystalline support (10). A single crystal CdTe substrate (5) is first epitaxially grown to a thickness of between 1 micron and 5 microns onto the support (10). Then a HgTe source (3) is spaced from the CdTe substrate (5) a distance of between 0.1 mm and 10 mm. The substrate (5) and source (3) are heated together in a thermally insulating, reusable ampoule (17) within a growth temperature range of between 500.degree. C. and 625.degree. C. for a growth time of between 5 minutes and 13 hours. In a first growth step embodiment, the source (3) and substrate (5) are non-isothermal. In a second growth step embodiment, the source (3) and substrate (5) are isothermal. Then an optional interdiffusion step is performed, in which the source (3) and substrate (5) are cooled within a temperature range of between 400.degree. C. and 500.degree. C. for a time of between 1 hour and 16 hours.

Abstract: A subsurface zener diode is formed in an N.sup.- epitaxial region formed on a P type substrate. The N.sup.- epitaxial region is isolated by a P.sup.+ isolation region. An N.sup.+ buried layer region is disposed between a portion of the N.sup.- epitaxial region and the P type substrate. A first P.sup.+ region is formed in the middle of the N.sup.- epitaxial region at the same time as the P.sup.+ isolation regions. Second and third adjacent P.sup.+ regions also are formed in the N.sup.- epitaxial region adjacent to and slightly overlapping the first P.sup.+ region, all three P.sup.+ regions terminating at the N.sup.+ buried layer. An N.sup.+ region, formed during an emitter diffusion operation, has first and second opposed edges centered within the overlapping portions of the first, second, and third P.sup.+ regions. Two other opposed edges of the N.sup.+ region extend beyond the other edges of the first P.sup.+ region, forming N.sup.+ N.sup.- contacts to the N.sup.

Abstract: A gate structure for integrated circuits and more especially for photosensitive charge-transfer devices comprises elements of the gate-insulator-semiconductor type. The gate structure is constituted by a thin film-layer of transparent or semi-transparent conductive material covered with a layer of compatible insulating material having a refractive index higher than 1.5.

Abstract: The invention relates to a protective arrangement for field-effect transistors with an insulated gate electrode. An integrated, indiffused protective diode whose breakdown voltage is smaller than that of the gate insulating layer is used therefor. The gist of the invention is that the breakdown voltage of the protective diode is set by two implantation processes, one of which is substantially limited to the region containing the in-diffused diode and the other of which substantially covers the surface of the substrate other than at least the channel region of the field-effect transistor so as to simultaneously increase the field inversion voltage.

Abstract: A layout for random logic in which different stages are assigned to columns according to the flow of logic signal. Each stage may consist of several parallel logic blocks defining a logic function and having an output. The logic blocks are implemented by several diffusion areas, not necessarily contiguous. The output line of a logic block is aligned vertically to match one or more gate electrodes of following stages that it drives. The interconnection to the following stages can be implemented by a single horizontal polysilicon line which also functions as the gate electrodes. The breaks in the diffusion of a logic block can accommodate the passage of polysilicon lines not being used in that logic block.

Abstract: Method of diffusing zinc into gallium arsenide and aluminum gallium arsenide. A wafer of gallium arsenide or aluminum gallium arsenide is placed in close proximity to a quantity of granular zinc gallium arsenide. The assemblage is heated in an open-tube furnace in the presence of flowing nitrogen to vaporize zinc whereby zinc diffuses into the gallium arsenide or aluminum gallium arsenide wafer without eroding the surface.

Abstract: Formation of an integrated circuit device with the trench isolation process is disclosed. A plurality of circuit elements such as transistors are isolated from one another by trenches formed in field isolation regions of a semiconductor substrate. Each trench should be filled with appropriate materials to maintain the flatness of the surface of the substrate. Borophosphosilicate glass (BPSG) is employed as the material filled into each trench.

Abstract: A solid-state imaging device having a scanning circuit and a photoconductive film formed in layers on a semiconductor substrate, and a process for forming the same, wherein high resolution with substantially no color mixing is attained. An electrode layer is formed over the semiconductor substrate for providing the plural electrodes, and a photoconductive film is formed over the electrode layer. A first transparent electrode is produced over the photoconductive film, after which a resist pattern is formed on the first transparent electrode layer corresponding to the pixels. The first transparent layer and the photoconductive film are etched according to the resist pattern to spatially isolate adjacent pixels in the first transparent layer and the photoconductive film. Adjacent pixels are isolated by etching, using the resist pattern, that part of the electrode layer on which are disposed the first transparent electrode layer and the photoconductive film between isolated pixels.

Abstract: A method of fabricating a semiconductor device includes the steps of: forming at least one first semiconductor region of a first conductivity type and at least one second semiconductor region of a second conductivity type in a main surface of a semiconductor layer of the first conductivity type; forming a three-layer film having a desired shape on each of the first and second semiconductor regions, the three-layer film being made up of a bottom layer which is a conductive film, an intermediate layer which is a silicon nitride film, and a top layer which is a polycrystalline silicon film doped with one of arsenic and phosphorus; forming a first insulating layer on the side wall of the three-layer film; forming a second polycrystalline silicon film on the whole surface, and diffusing one of arsenic and phosphorus from the first polycrystalline silicon film into the second polycrystalline silicon film; selectively etching off the first polycrystalline silicon film and that portion of the second polycrystalline s

Abstract: A process for the simultaneous production of bipolar transistors and complementary MOS transistors on a common silicon substrate wherein to accommodate the p-channel transistors, n-doped zones are produced in a p-doped substrate and npn bipolar transistors are provided in the n-doped zones where the n-zones form the collector of the transistor and the n-zones are superimposed over n.sup.+ -doped zones. The latter are connected in the bipolar transistor zone by deeply extending collector terminals. The use of sidewall insulation on the p.sup.+ - and n.sup.+ -conducting structures composed of polysilicon or a silicide which are used for diffusing-out source/drain zones and base-emitter zones permit the formation of shorter channel lengths. The process is used to produce VLSI circuits which have high switching speeds.

Abstract: In a process of fabricating a semiconductor IC device, a semiconductor substrate (1) having a first region (3) of a first conduction type which is electrically isolated is prepared, on which a polycrystalline semiconductor layer, and oxidation-resistant layers (8.sub.1, 8.sub.2) are formed in turn. In part of the first region that is not covered by the oxidation-resistant layers, second regions (6.sub.2, 6.sub.2) of a second conduction type are formed. Parts of the polycrystalline semiconductor layer that are not covered by the oxidation-resistant layers are selectively oxidized. After removal of the oxidation-resistant layers, an impurity of the second conduction type is introduced in the polycrystalline semiconductor layers, and is diffused therefrom into parts of the first regions beneath them to form therein a third region (10) and a fourth region (6.sub.1) of the second conduction. Selected parts of the surfaces of the polycrystalline layers are exposed.

Abstract: A bipolar/CMOS process includes bipolar transistors having emitters formed in less than a minimal masking dimension. An opening is formed through a polycrystalline silicon layer deposited on a silicon substrate. After coating the sides of the opening with silicon dioxide, the intrinsic base region of the bipolar transistor and the emitter region are implanted. The extrinsic base is formed by outdiffusion from the polycrystalline silicon layer. The structure includes an epitaxial layer which is more strongly doped below its surface than at its surface to enhance the performance of CMOS transistors formed therein. Additionally, the bipolar and complementary MOS transistors are self-aligned to each other by the manner in which the buried layers are formed.

Abstract: After contact holes for the P- and N-type source or drain regions of P- and N-channel MOSFETs have been made at a common step, an N-type impurity is ion-implanted into at least the N-type source or drain regions through the contact holes. The N-type impurity is annealed to form an N-type region which is deeper than the N-type source or drain regions. During the annealing treatment, the N-type source or drain regions are covered with an insulating film.

Abstract: Process for producing temperature-stable undercut profiles for use in semiconductor fabrication. The process is based on the phenomenon of high etch-rate selectivity between RF- and LF- PECVD-grown silicon nitride films (12G and 13G, respectively) that are deposited on top of each other. By choosing proper film and process parameters, these PECVD nitride structures can be made stress-free: the tensile stress of the RF film (12G) compensates the compressive stress of the LF film (13G).Also disclosed is an application of a T-shaped structure (15), produced with the new process, in a method for fabricating fully self-aligned "dummy" gate sub-micron MESFETs.

Abstract: A semiconductor device, e.g., a complementary circuit comprising an n-channel transistor (Q.sub.n) utilizing a two-dimensional electron gas and a p-channel transistor (Q.sub.p) utilizing a two-dimensional hole gas, comprises: a semi-insulating GaAs substrate; a channel layer of an i-type GaAs having n.sup.+ -type source and drain regions and p.sup.+ -type source and drain regions; a buffer layer of an i-type AlGaAs preventing carriers from passing therethrough; first and second control layers of GaAs or AlGaAs having n-type or p-type conductivity, these layers being epitaxially formed in sequence on the substrate by an MBE method or an MOCVD method; and metal electrodes formed on the first and second control layers, n.sup.+ -type regions and p.sup.+ -type regions.

Abstract: A method of making a semiconductor device for producing or amplifying electromagnetic radiation, more particularly a semiconductor laser, has a substrate which has a mesashaped raised portion. On either side of the mesa there is located a blocking layer of a conductivity type opposite to that of the substrate. On the blocking layer are formed a first passive layer of the same conductivity type as the substrate, an active layer and a second passive layer of a conductivity type opposite to that of the substrate. According to the invention, the blocking layer also extends over the mesa, which is connected by diffusion from at least the first passive layer to the blocking layer.