Abstract: A method of variably exposing photosensitive material. A semiconductor wafer is provided. A first target region and a second target region are identified on the semiconductor wafer. Photosensitive material is provided on the semiconductor wafer. An illuminating system including a source of illumination is provided. A mask is provided between the source of illumination and the photosensitive material. The photosensitive material is illuminated through the mask with the illuminating system to provide in a single step of the illuminating system a first illumination dose to the first target region and a second illumination dose to the second target region. The first illumination dose differs from the second illumination dose. No further illumination dose is provided to equalize the first illumination dose and the second illumination dose.

Abstract: A capacitor structure or an array of capacitors and a method of fabricating the structure utilize the contours of a cavity created in a layer stack to form two three-dimensional electrode plates. The three-dimensional electrode plates reduce the lateral size of the capacitor structure. The fabrication of the capacitor structure is compatible to conventional CMOS processing technology, in which the resulting capacitor structure may become embedded in a CMOS device. As an example, the capacitor structure may be fabricated along with a MOS transistor to produce a one-transistor-one-capacitor nonvolatile memory cell. Preferably, the three-dimensional electrode plates are made of platinum (Pt) or iridium (Ir) and the capacitor dielectric is a ferrous-electric material, such as lead-zirconate-titanate (PZT) or barium-strontium-titanate (BST).

Abstract: An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

Abstract: A method including: forming doped regions on a monocrystalline substrate; growing an epitaxial layer; forming trenches in the epitaxial layer extending to the doped regions; anodizing the doped regions in an electro-galvanic cell to form porous silicon regions; oxidizing the porous silicon regions; removing the oxidized porous silicon regions to form a buried air gap; thermally oxidizing the substrate to grow an oxide region from the walls of the buried air gap and the trenches, until the buried air gap and the trenches themselves are filled.

Abstract: Disclosed are organic thin film transistors that can be either n-channel or p-channel transistors, depending on biasing conditions. Such transistors are expected to find wide use in complementary circuits. A specific embodiment of the inventive transistor comprises a 15 nm thick layer of &agr;-6T with a 40 nm thick layer of C60 thereon. The latter was protected against degradation by the ambient by means of an appropriate electrically inert layer, specifically by a 40 nm &agr;-6T layer.

Abstract: Method for dual damascene metallization of semiconductor workpieces which uses a process for creating an etch stop in an insulator thereby eliminating the need for deposition of an etch stop layer. Electron beam exposure is used to cure the insulator, or material having a low dielectric constant. Application of the electron beam to the low dielectric constant material converts the topmost layer of the low dielectric constant material to an etch stop layer, while rapid thermal heating cures the remainder of the low dielectric constant material. Creation of an etch stop layer in the low dielectric constant material can also be achieved by curing the low dielectric constant material using ion implantation.

Abstract: A plasma treated chemical vapor deposition (PTTCVD) method for depositing high quality conformal tantalum nitride (TaNx) films from inorganic tantalum halide (TaX5) precursors and a nitrogen containing gas is described. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). In a thermal CVD process, a TaX5 vapor is delivered into a heated chamber. The vapor is combined with a process gas containing nitrogen to deposit a TaNx film on a substrate that is heated to 300° C.-500° C. A hydrogen gas is introduced in a radiofrequency generated plasma to plasma treat the TaNx film. The plasma treatment is performed periodically until a desired TaNx film thickness is achieved. The PTTCVD films have improved microstructure and reduced resistivity with no change in step coverage. The deposited TaNx film is useful for integrated circuits containing copper films, especially in small high aspect ratio features.

Abstract: In a method of manufacturing a semiconductor device, after performing ion-implantation and before forming an oxide film, a silicon substrate is disposed within a furnace to undergo a heat treatment at a temperature equal to or higher than 950° C. for a specific time period (equal to or longer than 15 minutes). When performing the heat treatment and when raising a temperature up to the heat treatment temperature, oxygen is supplied together with nitrogen gas (inert gas). A supply amount of oxygen is controlled to be equal to or less than 5% when raising the temperature up to the heat treatment temperature, and to be equal to or less than 2% when performing the heat treatment. After the heat treatment, the oxidation film is formed. As a result, crystal defects (OSFs) are prevented from being produced on the silicon substrate surface.

Abstract: A plasma enhanced chemical vapor deposition (PECVD) method for depositing high quality conformal tantalum nitride (TaNx) films from inorganic tantalum pentahalide (TaX5) precursors and nitrogen is described. The inorganic tantalum halide precursors are tantalum pentafluoride (TaF5), tantalum pentachloride (TaCl5) and tantalum pentabromide (TaBr5). A TaX5 vapor is delivered into a heated chamber. The vapor is combined with a process gas containing nitrogen to deposit a TaNx film on a substrate that is heated to 300° C.-500° C. The deposited TaNx film is useful for integrated circuits containing copper films, especially in small high aspect ratio features. The high conformality of these films is superior to films deposited by PVD.

Abstract: A process for forming metal interconnect structures, and metal via structures, using electroplating, or electroless plating procedures, has been developed. The process features the use of disposable conductive layers, used as seed layers for the plating procedures. After formation of the desired metal structures, on the portion of seed layer, exposed in an opening in the photoresist shape, the photoresist shape, and the underlying portion of the disposable conductive layer, are removed, resulting in the desired metal structures.

Abstract: A method for making a ULSI MOSFET includes establishing a gate void in a field oxide layer above a silicon substrate, after source and drain regions with associated source and drain extensions have been established in the substrate. A gate electrode is deposited in the void and gate spacers are likewise deposited in the void on the sides of the gate electrode, such that the gate electrode is spaced from the walls of the void. The spacers, not the gate electrode, are located above the source/drain extensions, such that fringe coupling between the gate electrode and the source and drain extensions is suppressed.

Abstract: A method for forming an oxide layer on an electronic substrate such as a process of forming an ultra-thin gate oxide layer on a silicon wafer and an apparatus for executing for such method are provided. In the method, a moisture generator is continuously heated after a water vapor generating process is completed in order to prevent any residual moisture from condensing on an inner wall of the moisture generator. The method thus prevents additional water vapor from being communicated to an oxidation furnace and causing a continuous, undesirable growth of oxide on the wafers. The method may further be improved by flowing an inert gas into the oxidation chamber at a location adjacent to the oxidation chamber such that a substantially moisture-free inert gas flow may be flown into the chamber to improve the temperature uniformity in the chamber and to pressurize the chamber for preventing moisture or other contaminating gases from entering the chamber from the outside ambient.

Abstract: A memory cell structure for a semiconductor memory device and fabricating method thereof, which is suitable for DRAM memory devices of 256M or more capacity requiring a very high degree of integration, which comprises the steps of forming sequentially first and second random layers on a semiconductor substrate; patterning a first photoresist layer having a limited line width on the second random layer; patterning the second random layer using as a mask the patterned first photoresist layer; removing the first photoresist layer, and then patterning the second photoresist layer having the limited line width between the pattern of the second random layer; patterning the first random layer using as a mask the second photoresist layer which is so patterned so as to be placed between the pattern of the second random layer; and removing the second random layer and the second photoresist layer.

Abstract: An interlayer insulation film is deposited on a substrate in which a semiconductor element has been formed. A wiring groove is formed in the interlayer insulation film. A barrier layer, made of a material which prevents the diffusion of Cu atoms, is formed on at least the inner surface of the wring groove and the upper surface of the interlayer insulation film. A seed layer, made of Cu which contains an impurity, -is deposited on the barrier layer. By way of plating, a conductive layer made of Cu is deposited on the seed layer so as to fill the wiring groove. The substrate is heated to precipitate the impurity, contained in the seed layer, on at least an interface between the seed layer and the barrier layer. The conductive layer, the seed layer and the barrier layer are removed until the upper surface of the interlayer insulation film appears, thus performing surface planarization.

Abstract: In accordance with one implementation the invention, a capacitor comprises two conductive capacitor electrodes separated by a capacitor dielectric layer, with at least one of the capacitor electrodes comprising at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. In accordance with another implementation, integrated circuitry includes a conductive silicon containing electrode projecting from a circuit node. A capacitor is received over the silicon containing electrode and comprises a first capacitor electrode having at least one of Pt and Pd, and also comprising another metal which is capable of forming a conductive metal oxide when exposed to oxidizing conditions. A high K capacitor dielectric layer received over the first capacitor electrode. A second capacitor electrode is received over the high K capacitor dielectric layer.

Abstract: A surface portion of a p type base region is made amorphous as an amorphous layer by implanting nitrogen ions which serve as impurities and ions which do not serve as impurities. After that, the amorphous layer is crystallized to have a specific crystal structure through solid-phase growth while disposing the impurities at lattice positions of the crystal structure. As a result, a surface channel layer is formed with a high activation rate of the impurities.

Abstract: The method of the present invention is directed to the formation of an arsenic silicon glass (ASG) film onto a silicon structure and finds a valuable application in the buried plate region formation process in the manufacture of deep trench cell capacitors in EDO and SDRAM memory chips. The starting structure is state-of-the-art and consists of a silicon substrate coated by a patterned SiO2/Si3N4 pad layer which defines deep trenches formed therein by etching. At the beginning of the conventional buried plate region formation, the interior side walls of deep trenches are coated with an arsenic doped silicon glass (ASG) film resulting from the co-pyrolysis of TEOS and TEASAT in a vertical hot dual wall LPCVD reactor as standard. According to the present invention, a flow of O2 is added which makes this co-pyrolysis of TEOS and TEASAT no longer interactive. As a consequence, the improved process is much better controlled than the conventional one.

Abstract: According to the present invention, a conductive pad for a self-aligned direct contact and a self-aligned buried contact is formed of a first pad and a second pad, in twice, wherein the self-aligned direct contact and the self-aligned buried contact connect respectively a bit line/storage electrode to a semiconductor substrate. The first pad and the second pad are formed by combining a reverse active type self-aligned contact (RAT-SAC), a contact type self-aligned contact (CT-SAC), and an epitaxial growth processes. Thus, it is prevented that a shoulder portion of a gate electrode is overetched to create electrical short of pad to gate, a size of a pad is limited to a spacing between gate electrodes, a pad and a semiconductor substrate are not electrically connected each other (not-open), and electrical connection is created by lack of margin between BCs, in case of using only one process selected from a group consisting of the RAT-SAC process, the CT-SAC process, and the epitaxial growth processes.

Abstract: A memory circuit that includes a series of parallel elongated diffusion bit lines and an array of 2-bit non-volatile memory cells connected between the diffusion bit lines. Column select circuits are located at the ends of the diffusion bits lines that selectively connect the diffusion bit lines to a bit line decoder circuit to read appropriate signals from selected memory cells. A series of metal jumpers extend over and connect the ends of the diffusion bit lines. By connecting both ends of the diffusion bit lines together, the metal jumpers allow the diffusion bit lines to be longer without increasing resistance, so that a single pair of column select circuit control a large number of memory cells to increase the area efficiency of the memory array. Conversely, the metal jumpers reduce the resistance in shorter diffusion bit lines, thereby increasing memory array endurance.

Abstract: A memory device having vertical transistors in accordance with the present invention includes an active area pad isolated from adjacent active area pads on all sides and having a set of trench capacitors associated therewith. The set of trench capacitors are coupled to the active area pad through vertical transistors. The active area pad is configured to connect the set of trench capacitors to a first contact. A gate conductor pad is disposed between a set of active area pads and adapted to activate at least one vertical transistor in each active area pad adjacent to the gate conductor pad. Each gate conductor pad is activated by a second contact such that when the gate conductor pad is activated through the second contact the at least one vertical transistor in each active area pad conducts to provide access to the trench capacitors and transfers a state between the first contact and the trench capacitors.