Abstract: A process for heat-treating a single crystal silicon wafer to dissolve agglomerated vacancy defects and to influence the precipitation behavior of oxygen in the wafer in a subsequent thermal processing step. The process includes subjecting the wafer to a heat treatment to dissolve agglomerated vacancy defects, rapid thermally annealing the heat-treated wafer to cause the formation of crystal lattice vacancies throughout the wafer and controlling the cooling rate of the annealed wafer to allow some, but not all, of the crystal lattice vacancies to diffuse to the front surface to produce a wafer having a nonuniform vacancy concentration with the concentration of vacancies in the bulk of the wafer being greater than the concentration in the surface layer.

Abstract: In a crystalline silicon body a shallow trench insulation is made by etching a groove and filling it with silicon oxide. Ridges of polysilicon are made on the surface of the silicon body by applying a layer of polysilicon and patterning it with a known technique. Spacers of silicon nitride are provided on the side walls of the polysilicon ridges. A first layer of silicon nitride, a second layer of TEOS and a patterned resist layer are applied. The TEOS layer is etched by immersion in a solution of 0.36% HF for 14 minutes. Subsequently, the resist is stripped in H2SO4 or peroxide. The silicon nitride layer is etched by immersion in phosphoric acid of 165° C. for 15 minutes using the TEOS layer as a mask. A titanium layer is applied. Subsequently, the body is rapidly heated to a temperature of 760° C. at which it is kept for 20 seconds. During this rapid thermal treatment titanium silicide is formed at locations where the titanium is in contact with silicon i.e.

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate and operates when supplied with appositive supply voltage and a circuit ground potential. The device has word lines, pairs of bit lines, data storage capacitors, and N-channel MOSFETs each having a gate connected to any one of the word lines and a source-drain path interposed between one of the paired bit lines on the one hand and a terminal of any one of the data storage capacitors on the other hand. A positive internal voltage higher than a circuit ground potential is generated and fed as a bias voltage to P-type regions wherein address selection MOSFETs of dynamic memory cells are formed.

Abstract: Methods of forming field effect transistors and related field effect transistor constructions are described. A masking layer is formed over a semiconductive substrate and an opening having sidewalls is formed therethrough. The opening defines a substrate area over which a field effect transistor gate is to be formed. A dopant of a first conductivity type is provided through the opening and into the substrate. Sidewall spacers are formed over respective sidewalls of the opening. Enhancement dopant of a second conductivity type which is different from the first conductivity type is provided through the opening and into the substrate. A transistor gate is formed within the opening proximate the sidewall spacers, and source/drain regions of the second conductivity type are diffused into the substrate operably proximate the transistor gate. The first conductivity type dopant forms a halo region proximate the source/drain regions and lightly doped drain (LDD) regions for the transistor.

Abstract: The object of the present invention is to provide an aluminum electrolytic capacitor and its manufacturing method. The aluminum electrolytic capacitor of the present invention comprises a capacitor element formed by winding an electrode foil, at least an anode foil of which is structured so as to have part of the surface thereof made free of an oxide film and connected with a lead. The capacitor element is placed in a bottomed metal case together with a driving electrolyte, thereby achieving low resistance, a reduction in size, high ripple-current carrying and low loss characteristics entirely due to perfect connection between the electrode foil and the lead.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.

Abstract: The present invention includes a method for bonding one semiconductor surface to a second semiconductor surface. The method includes providing a first article that has a semiconductor surface and a second article that has a semiconductor surface. The semiconductor surfaces are annealed with an energy source wherein energy is confined to the semiconductor surfaces. The annealed surfaces are bonded to each other.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A method for composing a dielectric layer within an interconnect structure of a multilayer semiconductor device is disclosed. A layer of silica precursor material is first deposited on a silicon substrate. Without affecting its structure and porosity, the layer of silica precursor material is then dried; and the layer of silica precursor material becomes porous silica film. Subsequently, a protective layer, such as parylene, is deposited on top of the dried porous silica film. The thickness of the protective layer should be greater than the peak-valley planarization requirements of the silicon substrate surface. As a result, a composite porous silica film, which services as a dielectric layer within an interconnect structure, is formed. This composite porous silica film has a relatively low dielectric constant and is able to withstand damage from a standard CMP procedure.

Abstract: A capacitor for a semiconductor device is disclosed with increased capacitance which is produced by a simplified manufacturing process. The capacitor has a storage node electrode structure formed on the semiconductor device having impurity regions formed therein. The storage node electrode structure includes a buried layer formed in a storage node hole defined by the semiconductor device, the buried layer being in contact with at least one impurity region, a bottom layer formed on the buried layer and extending beyond the buried layer, a first cylindrical electrode having first walls upwardly extending from the bottom layer, and second cylindrical electrodes having second walls upwardly extending from the bottom layer and disposed on outer sides of the first cylindrical electrode.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide. The unreacted layer of metal is removed with the composite structure remaining as the local interconnect.

Abstract: A semiconductor device includes a semiconductor substrate having a trench on a surface thereof and an embedding member embedding the interior of the trench therewith. While the section of the trench when cut by a first plane perpendicular to the direction of the depth of the trench is defined as a first section and the section of the trench when cut by a second plane perpendicular to the direction of the depth of the trench and closer to the bottom of the trench than the first plane is defined as a second section, the area of the first section is smaller than that of the second section and a minimum radius of curvature of the first section is smaller than a minimum radius of curvature of the second section. As a result, it is possible to lessen the concentration of the electric field into the bottom of the trench.

Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.

Abstract: The semiconductor wafer is made thin without any cracks and warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier 1 formed of a base 1a and a suction pad 1b provided on one surface of the base 1a or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier 1 in such a manner that a rear surface of the semiconductor wafer 2 with no circuit elements formed therein is opposite to the carrier to form a wafer composite 10, and the third step of holding the carrier of the wafer composite 10 with its semiconductor wafer 2 side up and spin-coating an etchant on the rear surface of the semiconductor wafer 2 thereby to make the semiconductor wafer 2 thin.

Abstract: A small size electronic component has a small direct current resistance value of conductor pattern and minimal dimensional irregularity of a conductor pattern. In order to form such a component, a photosensitive conductive paste applied on a ceramic substrate and is then exposed through a photo mask and developed so as to form a lower conductor pattern layer of a coil conductor pattern. Then an insulating paste is applied on the ceramic substrate so as to cover the lower conductor pattern layer and the insulating paste is removed with a solvent until at least the upper surface of the lower conductor pattern layer is exposed so as to form an inter-line insulating layer. Furthermore, after applying a photosensitive conductive paste as a film, the exposure and development operation is conducted again while using the photo mask so as to form an upper conductor pattern layer on the lower conductor pattern layer.

Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

Abstract: A memory cell has a cylindrical electrode having a porous cylindrical portion, and insulating layers for making less steep the height of cylindrical electrode are provided in the peripheral circuit region. Thus a semiconductor memory device and manufacturing method thereof can be provided in which the step between the memory cell array region and the peripheral circuit region can be made less steep by a smaller number of manufacturing steps.

Abstract: A ferroelectric thin film capacitor has smooth electrodes permitting comparatively stronger polarization, less fatigue, and less imprint, as the ferroelectric capacitor ages. The smooth electrode surfaces are produced by DC reactive sputtering.