Abstract: A structure and method is disclosed for dissipating electrostatic charges comprising an underlying dielectric layer disposed over capacitor plates of sensor circuitry, and a conductive layer and passivation layers disposed over the underlying dielectric layer wherein the conductive layer diffuses electrostatic charges at the surface of the integrated circuit.

Abstract: An integrated circuit includes a substrate, and at least one copper interconnection layer adjacent the substrate. The interconnection layer further comprises copper lines, each comprising at least an upper surface portion including at least one copper fluoride compound. The copper fluoride compound preferably comprises at least one of cuprous fluoride and cupric fluoride. The compounds of copper and fluoride are relatively stable and provide a reliable and long term passivation for the underlying copper. In accordance with one particularly advantageous embodiment of the invention, the dielectric layer may comprise a fluorosilicate glass (FSG) layer. Accordingly, during formation of the FSG layer, the upper surface of the copper reacts with the fluorine to form the copper fluoride compound which then acts as the passivation layer for the underlying copper. In other embodiments, the dielectric layer may comprise an oxide or air, for example.

Abstract: A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, forming spacers along the side walls of the first aperture, creating a second aperture in the first insulating layer below the first aperture, and filling the aperture with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

Abstract: The via contact structure is rendered into a dual damascene type via contact structure having a wide groove and a via contact hole lying below the wide groove, and the interior of the lower via contact hole is filled up with a filling material composed of tungsten, while, the interior of the upper groove is filled up with aluminum. Since the interior of the lower via contact hole is thus filled up with a filling material comprising tungsten, aluminum which has a low reflowability may be used only in the upper groove. As for the filling material for filling up the wide groove, the wide groove can be filled up sufficiently well even with aluminum which is not high in reflowability. By combining the filling of the via contact hole with tungsten and the filling of the groove with aluminum as mentioned above, a via contact filling with a high aspect ratio can be realized.

Abstract: Using this special dual damascene process, interconnect conducting lines and via contacts are formed which have low parasitic capacitance (low RC time constants). The invention incorporates the use of thin etch stop or etch barrier layers. The key process steps of this invention are a special partial via hole etch and a special via hole liner. The Prior Art dual damascene processes are generally composed of a thick via etch stop layer to avoid damaging underlying Cu during via patterning, as well as, a thick trench etch stop layer to avoid via hole facet during trench patterning. Thick etch stop layers are undesirably due to high dielectric constant values compared with silicon oxide, the intermetal dielectric (IMD). Therefore, the thickness of stop-layer should be reduced to minimize the circuit (RC) time constant delay. In general, there are two main approaches for dual damascene etching.

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. An initial conductive layer is deposited over an insulating layer either before or after contact opening formation. The deposition process tends to block the contact mouth with a metal overhang, or cusp. After both conductive layer deposition and contact formation a portion of the initial conductive layer is removed, thus removing at least a portion of the metal cusp and opening the contact mouth for further depositions. The invention has particular utility in connection with formation of metal plugs in high-aspect ratio contacts. Embodiments are disclosed wherein the cusp removal comprises mechanical planarization, etching with high viscosity chemicals, and facet etching.

Abstract: A semiconductor device capacitor has a storage electrode wherein the impurity concentration decreases from the bottom to the top thereof. The semiconductor device capacitor is formed on a lower structure of a semiconductor substrate burying a contact hole formed on the semiconductor substrate. The impurity concentration linearly or non-linearly decreases going upward from the bottom of the contact hole to the top of the storage electrode. A method of manufacturing the semiconductor device capacitor also provides that the storage electrode is formed such that the concentration of impurities decreases linearly or non-linearly going upward from the bottom toward the top.

Abstract: A method of forming a damascene structure in a semiconductor device arrangement uses a low k dielectric material in an etch stop layer that overlays a metal interconnect layer. The etch stop layer protects the metal interconnect layer, made of copper, for example, during the etching of a dielectric layer that overlays the etch stop layer. Following the etching of the dielectric layer, which stops on the etch stop layer, the etch stop layer is then etched with a chemistry that does not damage the underlying copper in the metal interconnect layer. The lower dielectric constant material employed in the etch stop layer reduces the overall dielectric constant of the film, thereby improving the operating performance of the chip.

Abstract: A patterned film structure within a semiconductor device includes a pattern formed within a hardmask film, and a pattern formed within an underlying semiconductor or metal film beneath the hardmask film. The etch bias of both isolated and nested features formed within the patterned structure, is substantially the same with respect to a masking film formed over the hardmask film.

Abstract: A semiconductor device manufacturing method of the this invention having the step of forming an interlayer insulating film on a semiconductor substrate, the step of making interconnection groove in the interlayer insulating film, the step of filling the inside of the interconnection groove with a conductive film which is made of a first substance and is thicker than the depth of the interconnection groove, the step of thermally stabilizing the size of crystal grains in an Al film either at the same time or after the Al film has been formed, the step of forming a Cu film on the Al film, the step of selectively forming &thgr; phase layers in a crystal grain boundary of the Al film by causing Cu to selectively diffuse into the crystal grain boundary of Al film and of allowing the &thgr; phase layers to divide the Al film in the interconnection groove into fine Al interconnections shorter than the Blech critical length, and the step of removing the Al film and Cu film outside the interconnection groove.

Abstract: A semiconductor device is made up of a first insulating layer having a through hole; a first interconnection which comprises a first conductive layer, a first barrier layer, and a first main interconnection, and a second interconnection connected to one of the first conductive layer and the first barrier layer. Accordingly, the semiconductor device can avoid a problem so that the Cu of the first main interconnection transfers from a portion connected to the second interconnection due to cause electromigration, the connected portion becomes a void, and the first interconnection is disconnected to the second interconnection.

Abstract: An improved SALICIDE process is described wherein the transformation temperature to a lower resistivity suicide structure is reduced by first coating with a layer of a silicon-germanium alloy prior to the deposition of the titanium layer. Provided there is at least 40 atomic percent of germanium in the alloy a second RTA at a temperature no higher than about 650° C. may be effectively used. The resulting ternary alloy has a resistivity of about 15-20 microhm cm which corresponds to a sheet resistance of about 3-3.5 ohms per square. The ability to achieve low sheet resistance after annealing at such a low temperature becomes increasingly more important as device dimensions decrease since the second RTA becomes increasingly more likely to result in agglomeration of the silicidelayer.

Abstract: A semiconductor device has a device isolation oxide film, an interlayer insulating film, hydrogen barrier films, a lower electrode, a capacitor insulating film, an upper electrode, an interlayer insulating film and a wiring layer, formed on a silicon substrate. A gate electrode is formed on a gate oxide film between impurity diffusion regions in the silicon substrate. Further, a capacitor portion, comprising the lower electrode, the capacitor insulating film (ferroelectric or high dielectric substance) and the upper electrode, is completely covered with the hydrogen barrier films. The hydrogen barrier films prevent deterioration of the ferroelectric substance and the high dielectric constant material due to reducing conditions in a hydrogen atmosphere. Other device characteristics, however, are not adversely affected because only the capacitor portion is completely covered with the hydrogen barrier films.

Abstract: A self-repairing interconnection system and methods for forming the system are disclosed. The system includes a metal pathway adjacent a metal-doped chalcogenide material. The system is configured to repair defects in the metal pathway by donating metallic ions from the metal-doped chalcogenide material to the metal pathway.

Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.

Abstract: A selective metal layer formation method, a capacitor formation method using the same, and a method of forming an ohmic layer on a contact hole and filling the contact hole using the same, are provided. A sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium Ti or platinum Pt, by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500° C. or lower.

Abstract: A semiconductor device including: an insulated gate type transistor having a columnar semiconductor region formed on the main side of a semiconductor substrate, a gate electrode formed on the side surface of the columnar semiconductor region while interposing a gate insulating film and main electrode regions respectively formed on and formed below the columnar semiconductor region; and a memory element which is formed on the upper main electrode region and which can be broken electrically.

Abstract: A method of forming an insulating film on a surface of a substrate includes the steps of heating the substrate in a processing chamber in an atmosphere containing water vapor maintained at 900° C. or higher to form a first insulating film on a surface of the substrate; and cooling down the substrate in the presence of water vapor to a temperature of 600° C. or less at a temperature decreasing rate of 15° C./sec or more so as to limit a thickness of a second insulating film formed at an interface between the first insulating film and the substrate.

Abstract: A method for forming through a microelectronic layer a via contiguous with a trench. There is first provided a substrate. There is then formed over the substrate a first microelectronic layer. There is then formed upon the first microelectronic layer an etch stop layer. There is then formed upon the etch stop layer a second microelectronic layer. There is then formed over the second microelectronic layer a first patterned photoresist layer which defines the location of a via to be formed through the second microelectronic layer, the etch stop layer and the first microelectronic layer. There is then etched, while employing a first etch method which employs the first patterned photoresist layer as a first etch mask layer, the second microelectronic layer, the etch stop layer and the first microelectronic layer to form a corresponding patterned second microelectronic layer, patterned etch stop layer and patterned first microelectronic layer which define the via.

Abstract: An improved and new process for fabricating a planarized structure of copper or other conductive material embedded in low dielectric constant HSQ insulator has been developed. The planarizing method comprises the key step of forming a protective layer on the surface of a cured HSQ layer by treatment of the cured HSQ layer in either an NH3 plasma or a N2 plasma. The NH3 plasma or a N2 plasma treatment may be applied to the cured HSQ prior to or subsequent to etching holes in the cured HSQ. Following deposition of copper or other conductive material into holes etched in the HSQ layer, CMP is used to remove the copper or other conductive material from the surface of the cured and treated HSQ. The NH3 plasma or a N2 plasma treatment reduces the CMP removal rate of HSQ by a factor of 3 when using a CMP slurry designed to polish copper.