Abstract: A method for attaching a semiconductor die to a leadframe is provided. Also provided are an improved semiconductor package, and a system for performing the method. The method includes applying an instant curing adhesive, such as a cyanoacrylate monomer or anaerobic adhesive, to the leadframe or die, and then polymerizing the adhesive at room temperature and ambient atmosphere, to form a cured adhesive layer between the die and lead frame. A catalyst can be applied to the leadframe, to the die or to the adhesive, to initiate polymerization. In addition, fillers can be added to the adhesive to improve various electrical and physical characteristics of the resultant adhesive layer. The system includes a dispensing mechanism for dispensing the instant curing adhesive on the leadframe or die, and a die attach mechanism for positioning and placing the die in contact with the dispensed adhesive.

Abstract: A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations.

Abstract: A low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjacent the front surface of a silicon wafer. A low energy silicon implant is also performed to create a plurality of gettering sites closely adjacent the front surface. Subsequently, an epitaxial silicon layer is grown on the front surface.

Abstract: Quality of epitaxial semiconductor substrates treated by carbon gettering is evaluated precisely and quickly to use only good-quality ones for manufacturing good-property semiconductor devices, such as solid-state imaging devices. After carbon implanted regions and carbon non-implanted regions are made along the surface of a Si substrate by selectively ion-implanting carbon, a Si epitaxial layer is grown on the surface of the Si substrate to obtain a Si epitaxial substrate. Recombination lifetime or surface photo voltage is measured at a portion of the Si epitaxial layer located above the carbon non-implanted region, and the result is used to evaluate acceptability of the Si epitaxial substrate. Thus, strictly selected good-quality Si epitaxial substrates alone are used to manufacture solid-state imaging devices or other semiconductor devices.

Abstract: A semiconductor wafer is made thin without any cracks or warp under good workability. The semiconductor wafer thinning process includes the first step of preparing a carrier formed of a base and a suction pad provided on one surface of the base or formed of a base film with an adhesive, the second step of bonding a semiconductor wafer to the carrier in such a manner that a rear surface of the semiconductor wafer with no circuit elements formed therein is opposite to the carrier to form a wafer composite, and the third step of holding the carrier of the wafer composite with its semiconductor wafer side up and spin-coating an etchant on the rear surface of the semiconductor wafer thereby to make the semiconductor wafer thin.

Abstract: An improved capacitor for a semiconductor memory device for preventing a bridge between storage electrodes and enlarging a surface area of a capacitor can be manufactured by forming a second insulating layer on a first insulating layer including a plug, etching the second insulating layer to form a storage electrode opening by using a storage electrode formation mask until the plug and a part of the first insulating layer are exposed, forming a conductive spacer on the sidewalls of the storage electrode opening to connect electrically to the plug, and forming an HSG (hemispherical grain) layer on the surfaces of the conductive spacers and the plug. A capacitor according to the present invention enables the HSG layer to grow on an internal wall of a storage electrode, thereby preventing a micro-bridge between storage electrodes resulting from abnormal growth or over-growth of the HSG layer.

Abstract: Stress corrosion induced voiding of patterned metal layers is avoided or substantially reduced by removing etching residues before gap filling. Embodiments include etching an Al or Al alloy layer employing fluorine and/or chlorine chemistry, wet cleaning, treating with a nitrogen-containing plasma at a temperature of at least about 400° C. and gap filling with a dielectric material, e.g. HDP oxide by HDPCVD.

Abstract: A method for improving the adhesion, between an overlying insulator layer, and an underlying low K layer, used for forming a composite layer, damascene mask pattern, wherein the damascene mask pattern is used as an interlevel dielectric layer, between metal interconnect structures, has been developed. A treatment, comprised of aqueous NH4OH solutions, or of UV curing procedures, is performed on the top surface of the low K layer, prior to deposition of the overlying insulator layer. The treatment, resulting in a roughened top surface of the low K layer, allows removal of masking photoresist shapes, to be aggressively accomplished using wet strippers, without adhesion loss at the insulator—low K layer interface.

Abstract: The invention relates to a method of iteratively, selectively tuning the impedance of integrated semiconductor devices, by modifying the dopant profile of a region of low dopant concentration by controlled diffusion of dopants from one or more adjacent regions of higher dopant concentration through the melting action of a focussed heating source, for example a laser. In particular the method is directed to increasing the dopant concentration of the region of lower dopant concentration, but may also be adapted to decrease the dopant concentration of the region.

Abstract: A first contact hole for a bit line is formed in an interlayer insulating film, and a polysilicon film is formed on the inner surface of the contact hole and on the interlayer insulating film. Subsequently, the polysilicon film is subjected to isotropic dry etching using a resist as a mask, and the interlayer insulating film is subjected to RIE etching, thereby forming a second contact hole in the interlayer insulating film in a peripheral circuit region. Then, a laminated film is formed on the inner surface of the second contact hole and on the polysilicon film, and the second contact hole is filled with a filling member. The laminated film and the polysilicon film are patterned, thereby forming a bit line in a memory cell region.

Abstract: A method for forming a quaternary alloy film of Co—W—P—Au for use as a diffusion barrier layer on a copper interconnect in a semiconductor structure and devices formed incorporating such film are disclosed. In the method, a substrate that has copper conductive regions on top is first pre-treated by two separate pre-treatment steps. In the first step, the substrate is immersed in a H2SO4 rinsing solution and next in a solution containing palladium ions for a length of time sufficient for the ions to deposit on the surface of the copper conductive regions. The substrate is then immersed in a solution that contains at least 15 gr/l sodium citrate or EDTA for removing excess palladium ions from the surface of the copper conductive regions.

Abstract: A method of fabricating a contact of a semiconductor memory device to prevent severe necking of a storage node despite misalignment thereof, and thus to prevent the falling-down of the storage node. A portion of a contact hole is filled with a material having an etch selectivity with respect to the storage node above the material and with respect to a conductive layer beneath the material.

Abstract: In a semiconductor integrated circuit device having laser-trimmable fuses and a trimming position pattern, in order to increase trimming accuracy and reduce the size of the positioning pattern, the fuses and the positioning pattern are formed using the same thin film. The trimming positioning pattern has an abrupt boundary between a high light reflectivity region and a low reflectivity region so that light reflectivity varies abruptly. To further reduce size, the trimming positioning pattern can be formed in pad areas of a integrated circuit chip or placed at intersections between scribe lines in a wafer.

Abstract: A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses hardmask formed of carbon enriched titanium nitride. The hardmask has a high selectivity for etching contact and via openings in relatively thick insulative layers. The high selectivity requires a relatively thin hardmask which can be readily patterned by thin photoresist masks, making the process highly desirable for DUV photolithography. The hardmask is formed by MOCVD using a metallorganic titanium precursor. By proper selection of the MOCVD deposition conditions, a controlled amount of carbon is incorporated into the TiN film. The carbon is released as the hardmask erodes during plasma etching and participates in the formation of a protective polymer coating along the sidewalls of the opening being etched in the insulative layer.

Abstract: The present invention pertains to a carrier layer and a contact enabled by the carrier layer which enables the fabrication of aluminum (including aluminum alloys and other conductive materials having a similar melting point) electrical contacts in multilayer integrated circuit vias, through holes, or trenches having an aspect ratio greater than one. In fact, the structure has been shown to enable such contact fabrication in vias, through holes, and trenches having aspect ratios as high as at least 5:1, and should be capable of filing apertures having aspect ratios up to about 12:1. The carrier layer, in addition to permitting the formation of a conductive contact at high aspect ratio, provides a diffusion barrier which prevents the aluminum from migrating into surrounding substrate material which operates in conjunction with the electrical contact.

Abstract: The invention is directed to the use of copper as via and interconnect structures for an integrated circuit. The process in accordance with a preferred embodiment produces an interconnect layer of continuous copper with superior adhesion while requiring only a minimum number of steps for its production. This process addresses the current need in semiconductor manufacturing for reliable and performance-oriented vias and interconnect structures, while not being susceptible to many of the problems which plague the use of aluminum for similar structures. Fabrication of an integrated circuit in accordance with a preferred embodiment of the invention begins with the formation of semiconductor devices on a silicon wafer. Next, an intermetallic dielectric layer (IDL) is formed by materials such as silicon dioxide (SiO2), polymide, or silicon nitride over the devices. This step is followed by the laying of a diffusion barrier layer on the IDL surface.

Abstract: A semiconductor fabrication process in which enhanced salicidation and reliability is achieved by implanting a silicon bearing species and a nitrogen bearing species into the source/drain regions and polysilicon regions of an integrated circuit transistor prior to the silicide formation sequence. A gate dielectric is formed on an upper surface of a semiconductor substrate. The substrate includes an active region that is laterally disposed between a pair of isolation structures. The active region includes a channel region that is laterally disposed between a pair of source/drain regions. A conductive gate structure is formed on the upper surface of the semiconductor substrate aligned over the channel region A silicon bearing species is then implanted or otherwise introduced into the conductive gate structure and into the source/drain regions to form amorphous silicon rich regions proximal to respective upper surfaces of the source/drain regions and the conductive gate structure.

Abstract: A method of manufacturing a barrier metal film of a semiconductor device includes, after a barrier metal film is annealed, performing an oxygen-annealing in-situ immediately after the annealing. By forming the barrier metal film in this way, an amorphous oxide film is formed only at a predetermined depth from the surface of the barrier metal film, so that a junction spike caused by the diffusion of interconnection material into the barrier metal film can be effectively prevented. This method of manufacturing may also be used when manufacturing an interconnection film of a semiconductor device.

Abstract: A process for forming a local interconnect includes applying a layer of metal over a semiconductor layer. A layer of metal silicide is formed over the layer of metal. The layer of metal silicide is patterned to define the boundaries of the local interconnect. The metal silicide is reacted with the layer of metal to form a composite structure. The composite structure includes the metal silicide, another metal silicide formed as silicon from the metal silicide reacts with the underlying layer of metal and an intermetallic compound of the metal from the layer of metal and metal from the layer of metal silicide.

Abstract: A tPEN layer (108) having a tensile stress is formed over a conductive gate stack (104-106) provided on a semiconductor substrate. Following the formation of the conductive gate stack (104-106), an anneal is performed. The conductive gate stack includes a metal layer to prevent outgassing and poly depletion during the anneal. Next, a photoresist layer (110) is formed and patterned to form a gate (122, 124).