Abstract: User-controlled targeted cache purging includes receiving a request to perform an operation to purge data from a cache, the request including an index identifier identifying an index associated with the cache. The index specifies a portion of the cache to be purged. The user-controlled targeted cache purging also includes purging the data from the cache, and providing notification of successful completion of the operation.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data memory. A connection identifier (ID), received in association with the access request; may include a buffer ID designating a buffer in the data memory in which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into the real address of the data memory, and accessing the data memory at a location corresponding to the real address. Different types of buffers, such as point-to-point, scatter, and gather buffers may be used, and different patterns, such as first-in-first out (FIFO), nested loop, matrix transforms may be used.

Abstract: A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.

Abstract: A method, system and computer program product for batched remapping of virtual memory addresses for garbage collection in a large object area. A mapping from a table having a first set of virtual memory addresses and sizes of non-contiguous, page-aligned large objects in a large object area to a remapping table having a second set of virtual memory addresses is determined. In a single batch, a request is received that includes the second set of virtual addresses and requests a remapping of the large objects to the second set of virtual memory addresses. The second set of virtual memory addresses is validated, and the large objects are remapped to the second set of virtual memory addresses according to the request. The remapping results in a compaction so that the large objects are contiguous in the large object area. The remapping does not require copying data in physical memory.

Abstract: Non volatile memories and methods of programming thereof are disclosed. In one embodiment, the method of programming a memory array includes receiving a series of data blocks, each data block having a number of bits that are to be programmed, determining the number of bits that are to be programmed in a first data block, determining the number of bits that are to be programmed in a second data block, and writing the first data block and the second data block into the memory array in parallel if the sum of the number of bits that are to be programmed in the first data block and the second data block is not greater than a maximum value. The first and second data blocks may or may not be adjacent data blocks. Improved programming efficiency may be achieved in a memory circuit when the maximum allowable current may be limited by the application or the size of a charge pump. Inverse data may be written in parallel if the sum is greater than the maximum value.

Abstract: “A disk drive is disclosed comprising a head actuated over a disk wherein a Native Command Queuing (NCQ) access command is received from a host. The NCQ access command comprises at least one logical block address (LBA) associated with a logical block, and a tag field for identifying the access command. The tag field is evaluated to determine a size of the logical block, and the logical block is transferred between the disk drive and the host. The logical block comprises user data and protection information for implementing end-to-end protection. The tag field comprises a tag number selected from a range of numbers, where the range of numbers comprise a first range of numbers for identifying a logical block comprising user data and protection information, and a second range of numbers for identifying a logical block comprising user data without protection information.

Abstract: A technique for triggering a system bus write command with user code includes identifying a specific store-type instruction in a user instruction sequence. The specific store-type instruction is converted into a specific request-type command, which is configured to include core permission controls (that are stored in core configuration registers of a processor core by a trusted kernel) and user created data (stored in a cache memory). Slave devices are configured through register space (that is only accessible by the trusted kernel) with respective slave permission controls. The specific request-type command is then transmitted from the cache memory, via a system bus. In this case, the slave devices that receive the specific request-type command process the specific request-type command when the core permission controls are the same as the respective slave permission controls. The trusted kernel may be included in a hypervisor or an operating system.

Abstract: A system and method for converting data from one format to another in a processing pipeline architecture. Data is stored in a shared cache that is coupled between one or more clients and an external memory. The shared cache provides storage that is used by multiple clients rather than being dedicated to separately convert the data format for each client. Each client may interface with the memory using a different format, such as a compressed data format. Data is converted to the format expected by the particular client as it is read from the cache and output to the client during a read operation. Bytes of a cache line may be remapped to bytes of an unpack register for output to a naïve client, which may be configured to perform texture mapping operations. Data is converted from the client format to the memory format as it is stored into the cache during a write operation.

Abstract: A system and method for data cache management are provided in which a request for access to data is, and a sample value is assigned to the request, the sample value being randomly selected according to a probability distribution. The sample value is compared to another value such as a previously stored sample value, and the data is selectively stored in the cache based on results of the comparison. If the requested data is not in the cache, the sample value may be compared with an extreme one of a plurality of sampled values such as the lowest sampled value. Each of the sampled values may be stored in a database, and the sampled values or the probability distribution may be changed over time to account for frequency of requests.

Abstract: In one embodiment, a method for managing information related to dirty data stored in an intermediate cache coupled to one or more clients and to an external memory includes receiving a dirty data notification related to dirty data residing in the intermediate cache, the dirty data notification including a memory address indicating a location in the external memory where the dirty data should be stored and a data type associated with the dirty data, and extracting a bank page number from the memory address that identifies a bank page within the external memory where the dirty data should be stored. The embodiment also includes incrementing a first count associated with a first entry in a notification sorter that is affirmatively associated with the bank page, determining that the dirty data has a first data type, and incrementing a second count associated with the first entry.

Abstract: Methods and systems are provided for geometry-based virtual memory management. The methods and systems use Boolean space algebra operations to manage allocation and deallocation of tiled virtual memory pages in a tiled virtual memory provided by a tiled virtual memory subsystem. A region quadtree may be maintained representing a current allocation state of tiled virtual memory pages within a container. The region quadtree may be used to locate a rectangle or two dimensional (2D) array of unallocated tiled virtual memory pages, and physical memory pages may be mapped to tiled virtual memory pages in the rectangle by updating a lookup table used to translate tiled virtual memory page addresses to physical memory page addresses. A union or intersection of region quadtrees may be performed to generate a new region quadtree representing a new current allocation state of the tiled virtual memory pages.

Abstract: A method and system for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The method includes generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus, and causing the snoop request to be transmitted over the serial interface bus to a second processor. The method further includes extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.

Abstract: In a system and method for write hazard handling a memory management unit policy is pre-computed for a write request using an address that is at least one clock cycle before data. The pre-computed memory management unit policy is registered and used for controlling a pipeline stall to ensure that a non-bufferable write is pipeline-protected, so that no non-bufferable location is bypassed from within the pipeline, and so that a subsequent non-bufferable read will get data from a final destination. A read request is bypassed only after a corresponding write request is updated in a write pending buffer. The write request is decoded with the write request aligned to data. The write request is registered in the write pending buffer. Arbitration logic is allowed to force the pipeline stall for a region that will have a write conflict. Read requests are stalled to protect against write hazards.

Abstract: A system and method for cleaning dirty data in an intermediate cache are disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.

Abstract: A communication process and system for communicating between communication participants (S1, S2, S3, S4) that are provided for control and/or monitoring of a technological process, the communication participants connected in communication with each other by way of a bus system (B) and can be identified using their addresses. Each communication participant manages a first group of references as so-called service access points (SAPs), and for at least one of the service access points, a second group of references is managed. Access to an individual reference from this second group of references is carried out using the address of the accessing communication participant. A source address lookup table may be provided to convert participant addresses into a unique natural number corresponding to a particular reference.

Abstract: A processor, apparatus and method for storing segment descriptors of different sizes in a segment descriptor table are disclosed. Smaller segment descriptors may be segment descriptors similar to the x86 architecture definition, and larger segment descriptors may be used to provide virtual addresses (e.g. base addresses or offsets) having more the 32 bits. By providing a segment descriptor table that stores different sized segment descriptors, maintaining multiple segment descriptor tables for different operating modes may be avoidable while providing support for segment descriptors having addresses greater than 32 bits. In one embodiment, the larger segment descriptors may be twice the size of the smaller segment descriptors. The segment descriptor table may comprise entries, each capable of storing the smaller segment descriptor, and a larger segment descriptor may occupy two entries of the table.

Abstract: An apparatus and method for creating and maintaining a cyclic or circular buffer are implemented using logical blocks corresponding to the physical blocks of the buffer. The logical blocks are mapped to the physical blocks of the cyclic buffer, and are used to create an index table for the buffer. Each entry in the index table corresponds to one or more blocks in the buffer, and has a logical block number respectively associated with a buffer block. When information from the buffer is accessed, the index table is consulted to determine if the requested information is stored in the buffer. If the information is stored in the buffer, the logical block number corresponding to the information is retrieved from the entry and translated into a corresponding physical block number. Using logical block numbers allows simple determination of whether the buffer block is valid, and how new or fresh the buffer block is without requiring a generation or cycle number.

Abstract: A method is disclosed for managing pages of a designated memory object according to selected memory management policies. A user of the computer stores a table of selections in a memory of the computer, each selection indicating a memory object and one of at least two memory management policies for the memory object. The selections may select from one or more choices: e.g., whether pages of the memory object are to be reserved, or faulted on demand; whether pages of the memory object are to be locked into the memory of the computer, or to be demand paged from a fluid page pool; whether pages allocated for the memory object are to be zeroed; whether the memory object is to be mapped using shared page tables; or specifying the number of levels of translation pages of a designated memory object to be shared or whether memory for the memory object is to be allocated contiguous pages of memory. A symbolic name is assigned to each of the memory objects.

Abstract: A method, apparatus and computer program product for performing an instant copy of data are provided to support dynamically changeable virtual mapping schemes in a data processing system. The present invention separates processing of data unit requirements from the selection of which storage subsystems to use for storage by using a storage methodologies inventory. Various instant copy mechanisms are provided for copying data upon receiving a write operation to either original or copy data. The instant copy mechanisms may be selected based on the type of mapping originally used to store the data that is to be copied. Determining the mapping of the data may include parsing extents of the data into sets based on types of mapping used to map extents. The mapping of the data may be one of load point and offset, and a full pointer mapping.

Abstract: A method, system, apparatus and computer program product for reducing the number of physical storage systems needed for a volume group to remain active are provided. This is accomplished by creating mirroring sets out of the physical storage systems in the volume group and by setting up a policy that so long as one mirror out of each mirror set is available, the volume group should be allowed to remain active. To activate a volume group (i.e., when the computer system is turned or reset), there have to be at least one full mirror set and at least one mirror out of each remaining mirror set available. These two policies guarantee that there will always be valid metadata in the system.