Abstract: A system, method and computer program product for synchronizing data written to tape so that the data can be recovered in case of failure. When writing data to tape, an index is kept in memory and updated to reflect change(s) to a file system mounted on tape. After a predetermined amount of data is written to a tape, a device may perform a sync operation, causing the index to be written into a data partition of the tape. If the sync operation is successful, the index in the index partition of the tape can be updated using a copy of the index in the data partition of the tape next time the tape is mounted. If the sync operation is not successful, the device may write the data to a different location on the same or another tape, update the index, and force another sync operation. This process can be repeated.

Abstract: A command processing pipeline is coupled to a shared cache. The command processing pipeline comprises (i) a first command processing stage configured to sequentially receive and process first and second cache commands, and (ii) a second command processing stage coupled to the first command processing stage. The first and the second command processing stages are two consecutive command processing stages of the command processing pipeline. The first and second command processing stages may access different groups of cache resources, and the first and second cache commands may be processed during consecutive clock cycles of a clock signal. Processing of the second cache command may be performed independently of an outcome of processing the first cache command by the first command processing stage. A third command processing stage may write data associated with the first cache command to one of a valid memory and a data memory included in the cache.

Abstract: A data processing system that manages data hazards at a coherency controller and not at an initiator device is disclosed. Write requests are processed in a two part form, such that a first part is transmitted and when the coherency controller has space to accept data, the data and a state of the data prior to a write are sent as a second part of a write request. When there are copending reads and writes to the same address, writes are stalled by not responding to the first part of a write request and snoop requests received to the address are processed regardless of the fact that the write is pending. When the pending read has completed, the coherency controller will respond to the first part of the write request and the initiator device will complete the write by sending the data and a state indicator following the snoop.

Abstract: A method for cleaning dirty data in an intermediate cache is disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes may include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.

Abstract: A memory system includes: a cache memory, a nonvolatile semiconductor memory, and a controller. The controller includes a plurality of management tables that manage data stored in the cache memory and the nonvolatile semiconductor memory using a cluster unit and a track unit. The controller performs data flushing processing from the cache memory to the nonvolatile semiconductor memory when the number of track units registered in the cache memory exceeds a predetermined threshold. Data may be flushed to the nonvolatile memory in different size data units such as a cluster or a track. Data flushing processing may also be performed if a last free way is used when data writing processing is performed on the cache memory managed in a set associative system. The nonvolatile semiconductor memory can be a NAND flash memory.

Abstract: A technique for ensuring that multiple producer threads may simultaneously write entries in a shared queue and one or more consumers may read valid data from the shared queue. Writing of the shared queue by the multiple producer threads may occur in parallel and the one or more consumer threads may read the shared queue while the producer threads write the shared queue. A “wait-free” mechanism allows any producer thread that writes a shared queue to advance an inner pointer that is used by a consumer thread to read valid data from the shared queue. The inner pointer indicates the most recent valid entry. An output pointer is advanced with an atomic operation to indicate a next entry or portion of memory in the shared queue that is available for allocation. The shared queue may be implemented as a circular buffer.

Abstract: A method for managing data movement in a multi-level cache system includes selecting at least one outgoing data block from a primary cache when an unallocated space of the primary cache has reached a minimum threshold, initiating a de-stage process for de-staging the outgoing data block, and terminating the de-stage process when the unallocated space has reached an upper threshold. The de-stage process includes storing the outgoing data block in a secondary cache when a cache hit has occurred before. The cache hit may be an actual cache hit or a “ghost” cache hit wherein only metadata is stored in the secondary cache. A method for de-staging an outgoing data block from a higher level cache which includes storing an outgoing data block in a lower level cache when a cache hit rate satisfies a predetermined condition and storing metadata in the lower level cache is also disclosed.

Abstract: Methods and apparatus relating to processing out of order transactions for mirrored subsystems. A first device (that is mirroring data from a second device) includes a cache to track out of order write operations prior to writing data from the write operations to memory. A register may be used to track the state of the cache in response to receipt of a special transaction, which may be a posted transaction or snapshot. The first devise transmits an acknowledgement of commitment of the data to memory once all cache entries, as recorded at a select point by the register, are emptied or otherwise invalidated. Devices may communicate via a peripheral component interconnect express (PCIe) interconnect, and may include a point-to-point or serial link. Various components may be on the same integrated circuit die. An uninterrupted power supply or batteries may supply power in response to a power failure.

Abstract: An electronic device having one or more services made available to a host equipment with which it is connected. The device automatically adjusts the access capability to the services made available depending on the software platform available within the host equipment. The electronic device may include a platform identifier operating on data exchanged with the host equipment to identify the platform. The electronic device may be an electronic storage device providing access capability for reading/writing to memory, wherein the access capability is adapted to the host equipment. A memory may be partitioned into areas of memory dedicated to first and second types of software platforms available within the host equipment, and an area independent of the type of software platform. A memory may also be operated to list services authorized for a given platform, wherein a reference to this memory may be contained in a reserved memory.

Abstract: A data storage device and methods of performing memory operations using location-based parameters are disclosed. A method includes identifying a set of parameter values associated with a physical block of a memory array on a memory die. The set of parameter values is identified based on a physical location of the physical block. A physical location may include an edge or a central region of the memory array or the memory die. The memory die may comprise a nonvolatile semiconductor memory (e.g., flash memory). Parameter values may include a size or a number of programming steps, pulse widths, maximum programming or erase voltages, reading or verify reference voltages, and parameters relating to error correction, among others, including time dependent parameters. A memory access operation, such as a reading, programming, or erasing operation, is initiated with respect to the physical block in accordance with the set of parameter values.

Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.

Abstract: System and method for an information security device with a compact flash (CF) interface are disclosed. The information security device determines an object being operated according to an instruction sent by a host using a card reading apparatus, and performs a flash memory operation or an information security operation. The determining by the information security device of the object being operated by the host includes the control chip of the information security device determining whether the object being operated by the host with the card reading apparatus is a real section or a virtual section inside the device, wherein the real section refers to the section in the flash module of the information security device, and the virtual section is predefined in the information security chip in the information security device.

Abstract: A system, method and computer program product for detecting an additional storage device within an “n” device array. The “n” device array is configured to store “n” device array formatted data. The “n” device array is reconfigured into an “n+m” device array. The “n” device array formatted data is written to the “n+m” device array in an “n+m” device array format. Reconfiguring the “n” device array may include converting the “n” device array formatted data into “n+m” device array formatted data. The “n+m” device array may comprise two storage devices including a mirrored storage device, or may include at least three storage devices including a coded target storage device such as a parity storage device. The coded target storage device may be a distributed coded target as in a RAID array.

Abstract: An apparatus and method for preventing FIFO overflow and underflow are disclosed. The apparatus includes a memory block, a write address control configured to generate a write address for writing data to the memory block at a write rate, a read address control configured to generate a read address for reading data out of the memory block at a read rate, and a management controller configured to adjust one of the write rate and the read rate to track the other rate based on a difference between the write address and the read address, for example by dynamically adjusting the read rate to the write rate. A direction in which the difference changes may also be detected. The memory block may be configured as a dual-port memory block. An audio apparatus including a digital audio input and output and a buffer is also disclosed.

Abstract: A management server and a data migration method shorten a data backup processing time and improve the efficiency of data duplicate removal in a storage apparatus. The management server includes a backup capacity calculation unit for calculating, based on duplicate information of data stored in a plurality of storage apparatuses, a backup capacity of the data if duplicate data is removed. The management server includes a migration source data determination unit for determining, based on the calculated backup capacity, data which is a target for migration to another storage apparatus among data stored in one of the storage apparatuses. The management server further includes a migration destination storage apparatus determination unit for determining, based on duplicate information of the migration target data and data of a storage apparatus which is a migration destination for the data, a migration destination storage apparatus for the data.

Abstract: Techniques are disclosed for maintaining cache coherency across a serial interface bus such as a Peripheral Component Interconnect Express (PCIe) bus. The techniques include generating a snoop request (SNP) to determine whether first data stored in a local memory is coherent relative to second data stored in a data cache, the snoop request including destination information that identifies the data cache on the serial interface bus and causing the snoop request to be transmitted over the serial interface bus to a second processor. The techniques further include extracting a cache line address from the snoop request, determining whether the second data is coherent, generating a complete message (CPL) indicating that the first data is coherent with the second data, and causing the complete message to be transmitted over the bus to the first processor. The snoop request and complete messages may be vendor defined messages.

Abstract: A computer system and a storage migration method capable of simplifying the migration process of a storage apparatus while avoiding the performance degradation of the overall system. A management apparatus for managing data migration from a first storage apparatus to a second storage apparatus is provided.

Abstract: A data management system and method for storing data records of at least two different category types in a first non-volatile memory section, which may be flash memory, divided into sequentially arranged memory locations. The data records, each including its category type and a time stamp, are sequentially stored into memory locations indicated by a cyclic write pointer stored in a second nonvolatile memory section. A new node associated with a data record is added to a linked list stored in a volatile memory section for a determined category type, such that there is a separate linked list for each category type. The data management system may be included in a glucose meter of a blood glucose system, and use of the second nonvolatile memory section and the volatile memory sections allows data records stored in the first nonvolatile memory section to be displayed by category type and by time stamp more quickly.

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: A storage apparatus includes a microprocessor package configured to access a logical volume and a local memory in the microprocessor package. An input/output (I/O) request range of one I/O request, including a start position address and an end position address of the logical volume which is a target of the one I/O request, is stored in the local memory. A counter value indicating a number of I/O requests to and from the logical volume associated with the one I/O request is acquired and stored in the local memory. If the counter value associated with the one I/O request is greater than the counter value associated with another I/O request, the I/O request ranges of the one I/O request and the other I/O request are compared. If there is no overlap between the I/O request ranges, the one I/O request is executed; otherwise, the one I/O request is placed on standby.