Abstract: A system and a method for managing an expansion read-only memory (ROM), and a management host thereof are provided. The management host is connected with a computer host through a bridge. The management host establishes an address lookup table to assign a virtual function and an expansion ROM corresponding to the virtual function. When a request is issued by the computer host to obtain a size of the expansion ROM, the management host provides data in a shadow register block corresponding to the expansion ROM to the computer host according to the address lookup table. The computer host assigns a memory block in the computer host to the expansion ROM according to the data in the shadow register block. When a request is issued by the computer host to obtain data of the expansion ROM through the bridge, the management host provides the data of the expansion ROM to the computer host according to the memory block.

Abstract: A processor includes at least one execution unit, a near memory, and memory management logic to manage the near memory and a far memory external to the processor as a unified exclusive memory. Each of a plurality of data blocks may be exclusively stored in either the far memory or the near memory. The unified exclusive memory space may be divided into a plurality of sets and a plurality of ways. In response to a request for a first block stored in the far memory, the memory management logic may move the first block from the far memory to the near memory, and may move a second block from the near memory to the far memory. A tag buffer may store tags associated with blocks being moved between the near memory and the far memory. Fill and drain buffers may also be used. Other implementations are described and claimed.

Abstract: A hardware SATA virtualization system without the need for backend and frontend drivers and native device drivers is disclosed. A lightweight SATA virtualization handler can run on a specialized co-processor and manage requests enqueued by individual guest devices or virtual machines (VMs). The lightweight SATA virtualization handler can also perform the scheduling or queuing of the requests based on performance optimizations to reduce seek time as well as based on the priority of the requests. The specialized co-processor can communicate to an integrated SATA controller through an advanced host controller interface (“AHCI”) data structure that is built by the coprocessor and has commands from one or more VMs. Guest devices or guest operating systems can build associated AHCI data structures in memory, which may be on-chip memory or DDR memory.

Abstract: Systems, apparatuses, and methods for improving transactional memory (TM) throughput using a TM region indicator (or color) are described. Through the use of TM region indicators younger TM regions can have their instructions retired while waiting for older TM regions to commit. A copy-on-write (COW) buffer may be used to maintain a mapping from checkpointed architectural registers to physical registers, wherein the COW buffer maintains a plurality of register checkpoints for a plurality of TM regions by marking separations between TM regions using pointers, a first pointer to identify a position in the COW buffer of the last committed instruction, a retirement pointer to identify a boundary between a youngest TM region and a currently retiring position.

Abstract: A search unit including a distributor TCAM and a DRAM search unit and a method to divide a database of TCAM rules is disclosed. The method includes selecting a rule having multiple “don't care” values and selecting a bit of the rule having a “don't care” value, generating two distributor rules based on the selected rule, associating rules of the database which match each of the distributor rules with the distributor rule they match to create subset databases, and repeating the steps of selecting, generating and associating until the average number of rules in each subset database is at or below a predefined amount. A DRAM storage unit has a section for each subset database, where each section is pointed to by a different distributor rule. A DRAM search unit matches an input key to one of the rules in the section pointed to by the matched distributor rule.

Abstract: A method and system for establishing more direct access to a storage device from unprivileged code are described. Using a storage infrastructure mechanism to discover and enumerate storage architecture component(s), a user mode application requests a portion of the storage device to store application-related data. That portion is mapped to an address space representing the application-related data. The storage infrastructure mechanism determines whether the user mode application is authorized to access the storage device and if satisfied, the storage infrastructure mechanism configures at least one path for the user mode application to perform block-level input/output between the storage device and an unprivileged storage architecture component. A completion notification mechanism may be selected or established for returning information related to input/output requests.

Abstract: A memory device includes a substrate, a plurality of nonvolatile memory chips disposed on the substrate, and a memory controller disposed on the substrate. The memory chips may be disposed on the same side or the opposite side of the substrate as the memory controller. The memory controller controls each of the nonvolatile memory chips based on a firmware, where the firmware is written in a nonvolatile memory chip positioned at a location farthest from the memory controller. A write system may perform writing using a binary or single level cell (SLC) recording system in memory chips located closest to the memory controller and a multi-value or multi-level cell (MLC) recording system in memory chips located farthest from the memory controller. A weighting factor may be assigned for each of the nonvolatile memory chips based on the distance from the memory controller.

Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Abstract: Methods and systems for providing a plurality of applications with concurrent access to data are disclosed. One such method includes identifying attributes of an expected data set to be accessed concurrently by the applications, initializing a shared cache with a column data store configured to store the expected data set in columns and creating a memory map for accessing a physical memory location in the shared cache. The method may also include mapping the applications' data access requests to the shared cache with the memory map. Only one instance of the expected data set is stored in memory, so each application is not required to create additional instances of the expected data set in the application's memory address space. Therefore, larger expected data sets may be entirely stored in memory without limiting the number of applications running concurrently.

Abstract: A cache memory system includes a cache memory including a plurality of cache memory lines and a dirty buffer including a plurality of dirty masks. A cache controller is configured to allocate one of the dirty masks to each of the cache memory lines when a write to the respective cache memory line is not a full write to that cache memory line. Each of the dirty masks indicates dirty states of data units in one of the cache memory lines. The cache controller may include a dirty buffer index which stores an identification (ID) information that associates the dirty masks with the cache memory lines to which the dirty masks are allocated. A cache line may include a fully dirty flag indicating when each byte in that cache line is dirty, so that a dirty mask does not need to be allocated for that cache line.

Abstract: A logical volume manager (LVM) may manage a plurality of logical volumes and a plurality of drives in a logical data storage using metadata stored on the plurality of drives. The metadata (e.g., global metadata) may include a first set of permissions for a storage location in one of the logical volumes. The LVM may analyze permission data (e.g., local permission data) associated with the storage location and may override the metadata (e.g., the permissions in the global metadata) with a second set of permissions obtained from the permission data. The LVM may use the second set of permission data to access the storage location (e.g., a logical volume, logical volume group, file, partition directory/folder, set of data blocks). Permission data may be generated based on an identifier for a virtual machine, computing device, or user, and may be generated based on user input.

Abstract: A system and method for managing program cycles in a multi-layer memory are disclosed. The method includes a controller receiving a request to program data from a host and, in advance of programming data associated with the request, determining a program cycle for programming the data associated with the request. The programming cycle may be a set of a host data write programming operation and any maintenance programming operations on an amount of data already programmed in the plurality of memory layers that is necessary to provide free memory capacity for a subsequent request to program data from the host. The controller programs the data associated with the host request, and the amount of data to be programmed in maintenance operations, in predetermined programming units according to the determined program cycle.

Abstract: A processing device and method for cache control including tracking updates to the line state of a cache superline are described. In response to a request pertaining to a superline, a cache controller of the processing device can perform one or more read-modify-write (RMW) operations to (a) a line state vector of a line state array and (b) a counter of the line state array. Based on a determination that one or more requests to the superline have completed, the line state vector from the line state array can be written to a tag array. The cache controller can track pending line state updates to a superline outside of the tag array, and a line state update can occur in the cache controller, rather than awaiting completion of all outstanding operations on a superline. Updates to multiple line states can be maintained simultaneously, and up-to-date ECCs computed.

Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses (LBAs) that are declared to be deleted by a user file management system. A plurality of data structures corresponding to levels of indirection are used to manage the mapping between a user logical block address and the physical location of the data in the flash memory system and to respond to user read and write requests by determining the current status of the user logical block address in the frame of reference of the memory system. This process substantially decouples TRIM management from garbage collection and wear leveling operations.

Abstract: A device can include an interface circuit configured to translate memory access requests at a controller interface of the interface circuit into signals at a memory device interface of the interface circuit that is different from the controller interface, the interface circuit including a write buffer memory configured to store a predetermined number of data values received at a write input of the controller interface, and a read buffer memory configured to mirror a predetermined number of data values stored in the write buffer memory; wherein the memory device interface comprises an address output configured to transmit address values, a write data output configured to transmit write data on rising and falling edges of a periodic signal, and a read data input configured to receive read data at the same rate as the write data.

Abstract: Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value, such as a log likelihood ratio (LLR), for a given bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the given bit in a given page of the one or more pages using the reliability value. The probability may be obtained from one or more transition probability tables, or may be based on one or more reference cells, prior decoded decisions or performance factors.

Abstract: A semiconductor memory device includes a memory which comprises a confidential information area storing confidential information and a flag. A controller reads the flag from the memory when instructed to erase or write data in the confidential information area, determines whether the flag is set, erases or writes data in the confidential information area when the flag is clear, and abandons a process requested by an erase or write instruction when the flag is set. An authenticator uses data in the confidential information area to execute an operation for authentication. A management information area may store management information for associated pages. The flag may include a bit string and a complementary bit string to improve reliability of the flag. The confidential information area may store dummy data when the memory is used for uses other than an application with an authentication function, so no problem arises using a normal controller.

Abstract: A system and method for determining soft read data for a group of cells in a nonvolatile flash memory are disclosed. An expected value representative of a plurality of stored values in a group of cells is obtained. A measured value representative of the plurality of stored values in the group of cells is obtained, based on a single read to the group of cells. A soft read data for the group of cells is determined based at least in part on the expected value and the measured value. The expected and measured values may include at least one of a number of 0s, a number of 1s, a ratio of 0s to 1s or a ratio of 1s to 0s. A reliability for a bit i may be obtained using a one-step majority logic decoder, and a threshold reliability may be used when determining the soft read data.

Abstract: A system, method and computer program product for synchronizing data written to tape with improved data recovery. When writing data to tape, an index is kept in memory and updated to reflect change(s) to a file system mounted on tape. After a predetermined amount of data is written to a tape, a device may perform a sync operation, causing the index to be written into a data partition of the tape. If the sync operation is successful, the index in the index partition of the tape can be updated using a copy of the index in the data partition of the tape next time the tape is mounted. If the sync operation is not successful, the device may write the data to a different location on the same or another tape, update the index, and force another sync operation. This process can be repeated.

Abstract: An intercluster repository synchronizer and method for synchronizing objects are disclosed. An example intercluster repository synchronizer includes an information processing system, including a processor, computer-readable medium, and network device. The intercluster repository synchronizer includes a structured information repository on the computer-readable medium. The structured information repository contains a plurality of records corresponding to a selected group of stored information objects. The intercluster repository synchronizer further includes a synchronization indicator that stores an address associated with a remote replication target. The intercluster repository synchronizer also includes a replicator, operable to send a message using the network device to the replication target responsive to changes in the structured information repository, and further operable to receive a message that a plurality of stored information objects have been duplicated at the remote replication target.