Abstract: A flash memory system having unequal number of memory die and method for operation are disclosed. The memory system includes a plurality of flash memory die distributed unevenly among different control lines, such that there are an unequal number of die between control lines. A total physical capacity of the plurality of flash memory die is greater than a total logical capacity such that the memory system is over provisioned with physical capacity. A logical address splitter directs data received from a host system and associated with host logical block addresses such that each control line only receives data associated with predetermined host logical block address ranges and directs the data such that a ratio of physical capacity to logical capacity is equal among each of the control lines, regardless of the different number of die and associated different physical capacity per control line.

Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.

Abstract: A solid state drive (SSD) interface controller includes a host interface, first and second command interfaces, and an interface information storage unit. The interface information storage unit is configured to store information for determining activation or deactivation of each of the first and second command interfaces, and a capacity allocated to each of the first and second command interfaces. The interface information storage unit may comprise first and second registers storing interface information, which may be changed in response to an extension ROM BIOS executed during a booting operation. The command interfaces may be configured to communicate using interface protocols such as SATA, SATA express, or nonvolatile express. An interface power management unit may cut power to an interface when deactivated based on the stored interface information.

Abstract: A system for distributing an available memory resource comprising at least two random access memory (RAM) elements and RAM routing logic. The RAM routing logic comprises configuration logic to dynamically distribute the available memory resource into a first memory area providing redundant memory storage and a second memory area providing non-redundant memory storage. The system may further comprise bus access ports which support at least one of concurrent access by a bus access port to access redundantly stored data or non-redundantly stored data, or concurrent access by at least two bus access ports to respective RAM elements to access redundantly stored data or to a respective one of the RAM elements to access non-redundantly stored data. Comparison logic and error detection or correction logic may be provided to detect or correct errors in information read from the RAM elements.

Abstract: A data storage device and method of accessing a word line of a memory array using values of one or more parameters based on a physical location of the word line. The method includes determining a block identifier of a physical block of a memory array that is to be accessed. The method further includes determining a word line index of a first word line within the physical block based on the block identifier and further based on a first position of the first word line within the physical block. The method further includes accessing the first word line using a first value of the first parameter.

Abstract: Systems and methods for retaining data in non-volatile solid-state memory are disclosed in which refresh copy operations are performed on data stored in non-volatile solid-state memory. A controller can comprise a data retention module configured to issue copy commands within different periods of time and to maintain usage data on a storage subsystem. A refresh copy operation helps ensure that data written to memory retain integrity by causing data to be programmed again onto the memory. Execution of refresh copy commands may be prioritized over other commands based on a remaining length of time. One or more data structures may be used to determine memory blocks that require refresh copy operations. In one embodiment, a validity bit array is used to track blocks that contain valid data. In another embodiment, a least recently used list is used to track blocks that have been least recently written.

Abstract: A semiconductor storage apparatus comprises a memory controller and flash memories which include a plurality of blocks as storage areas. The memory controller is configured to manage a degree of deterioration and read frequency for each of the plurality of blocks. A reliability maintained period is calculated for each storage area based on the degree of deterioration and read frequency for each storage area of a flash memory, and refresh is executed on each storage area in a planned manner based on the calculated reliability maintained period by newly storing the data stored in a block in another block based on an obtained reliability maintained period. The memory controller may also be configured to execute verification on each block and, if the number of failure bits is larger than a predetermined threshold, execute refresh to store data which is stored in a verification target block in another block.

Abstract: A solid state memory including a processor and a method for protecting the digital contents of the solid state memory. The microprocessor inserts at least an interruption during a copying or a reading of the digital contents and proceeds with the copying or reading only subsequent to a verification of a PIN or other user action. In particular, the verification provides control to ensure that the PIN is inserted manually. Access may be prevented if a time elapsed between the interruption and inputting of a PIN is shorter than a threshold time representing a speed of manual input, or if the PIN does not correspond to a sequence of requests for access to selectable files, which may be virtual files. The interruption may comprise substituting altered or cryptographic data if verification fails, or reproduction of an audio or visual message to be understood by the user.

Abstract: Storage devices herein include a non-volatile memory and a controller configured to perform a read operation on a physical page of the non-volatile memory in response to a read request on a logical page of the non-volatile memory from a host. The controller may include a mapping manager configured to manage a plurality of logical blocks by a logical unit. The mapping manager may include a unit map table including a correlation between the logical unit and a physical unit corresponding to the logical unit. Additionally, the mapping manager may be configured to change a mapping method according to whether the unit map table includes a physical unit corresponding to a logical unit including a logical page requested by the host. Related user devices and electronic devices are also provided.

Abstract: A system, method, and computer-readable storage media for disc identification are disclosed. A first disc format may be identified by matching a sequence of symbols on a disc to format data. Content stored on the disc in a first location that is used to generate IDs for the first disc format may be referenced, and the content processed to generate an ID for the disc. The first location can be identified by referencing ID processing data that also identifies other locations used to generate IDs for different disc formats. Portions of the content that are accessed can include directory names, folder names, or file names.

Abstract: A system and method for providing a faster disk recovery is provided by bypassing the file system cache temporarily holding a sub set of metadata objects of the file system and instead using a persistent fast storage that can be accessed at deterministic speeds to hold all the metadata objects of the file system. The system speeds recovery by only writing updated metadata objects to the persistent disk storage when file system recovery is complete.

Abstract: Methods and apparatus are provided for soft data generation for memory devices based on a performance factor adjustment. At least one soft data value is generated for a memory device, such as a flash memory device, by obtaining at least one read value; and generating the soft data value based on the obtained at least one read value and an adjustment based on one or more performance factors of the memory device. The read values may be soft data or hard data. Possible performance factors include endurance, number of read cycles, retention time, temperature, process corner, inter-cell interference impact, location and a pattern of aggressor cells. One or more pattern-dependent and/or location-specific performance factors may also be considered. The generated soft data value may be a soft read value used to generate one or more log likelihood ratios or may be the log likelihood ratios themselves.

Abstract: A memory system includes first and second districts, and a control section. Each of the first and second districts includes a memory cell array. The control section receives a single write command to simultaneously write first data to the first and second districts. A memory controller may subsequently issue a read command to read the first data from one of the memory cell arrays to determine whether the read first data is normal or is correctable based on a result of error correction in an error correction circuit. When the read first data is normal or is correctable, the first data written to the other of the memory cell arrays may be deleted or nullified.

Abstract: A method and apparatus use one or more inclusion bits and a victim bit to filter probes to shared caches. One embodiment of the method includes filtering a probe or snoop of one or more of a plurality of first caches based on a plurality of first bits, such as inclusion bits, associated with a line indicated by the probe or snoop. Each of the plurality of first bits is associated with a different subset of the plurality of first caches and each first bit indicates whether the line is resident in a corresponding subset of the plurality of first caches. A second bit, such as a victim probe bit, indicates whether the line is resident in more than one of the plurality of first caches in at least one of the subsets of the plurality of first caches. The first caches may be L1 caches and the first bits may be stored in an L2 cache of a multilevel cache.

Abstract: An apparatus including a snoop filter decoupled from a cache and an associated method for snoop filtering are disclosed. The snoop filter is decoupled from the cache such that the cache changes states of lines in the cache from a first state that is a clean state, such as an exclusive (E) state, to a second state that is not a clean state, such as a modified (M) state, without the snoop filter's knowledge. The snoop filter buffers addresses of replaced lines that are unknown to be clean until a write-back associated with the replacement lines occurs, or until actual states of the replaced lines are determined by the snoop filter generating a snoop. A multi-level cache system in which a reallocation or replacement policy is biased to favor replacing certain lines such as inclusive lines, non-temporal lines or prefetched lines that have not been accessed, is also disclosed.

Abstract: A method, system, and computer program product for selecting memory pages for compression based on a population count associated with their datasets are disclosed. For example, a dataset stored in a memory page of an uncompressed memory is analyzed. Based on the analyzing, a population count associated with the dataset is identified. The population count is compared to at least one threshold. Based on the comparing, the memory page is selected or rejected for compression.

Abstract: A semiconductor device having a circuit that selectively adjusts an impedance of an output buffer. A calibration operation can be performed automatically without issuing a calibration command from a controller. Because a calibration operation to a memory is performed in response to an auto refresh command having been issued for a predetermined number of times, a periodic calibration operation can be secured, and a read operation or a write operation is not requested from a controller during a calibration operation. A start-up circuit activates the calibration circuit when a refresh counter indicates a predetermined value, and prohibits a refresh operation in response to the auto refresh command when the calibration circuit is activated. A temperature detecting circuit may be used to change the frequency of performing a calibration operation.

Abstract: A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

Abstract: To ensure that the contents of a non-volatile memory device cache may be relied upon as accurately reflecting data stored on disk storage, it may be determined whether the cache contents and/or disk contents are modified during a power transition, causing cache contents to no longer accurately reflect data stored in disk storage. The cache device may be removable from the computer, and unexpected removal of the cache device may cause cache contents to no longer accurately reflect data stored in disk storage. Cache metadata may be managed during normal operations and across power transitions, ensuring that cache metadata may be efficiently accessed and reliably saved and restored across power transitions. A state of a log used by a file system may be determined prior to and subsequent to reboot of an operating system in order to determine whether data stored on a cache device may be reliably used.

Abstract: A disk drive is disclosed comprising a non-volatile write cache and a head actuated over a disk. A plurality of write commands are received from a host, wherein each write command comprises write data. A workload for a non-cache area of the disk is determined, and when the workload for the non-cache area of the disk is less than a threshold independent of a workload for the write cache, substantially all of the write data is stored in the non-cache area of the disk. When the workload for the non-cache area of the disk is greater than the threshold independent of the workload for the write cache, a first percentage of the write data is stored in the non-volatile write cache and a second percentage of the write data is stored in the non-cache area of the disk, wherein the first percentage is proportional to the workload for the non-cache area of the disk.