Abstract: A memory device and method for altering a performance characteristic of a memory array to increase a rate at which the memory device writes data in response to the memory device experiencing a demand for bandwidth above a threshold. The memory device may include a memory controller and a memory array, which may include memristive memory elements. To alter a performance characteristic, for example, the memristive memory elements may be written at sub-full resistive states which have a smaller difference between high and low resistive states, and/or the memory controller may disable a subset of memory elements and/or memory cells along a bit line and/or word line of the memory array. The subset of memory elements may be re-enable in response to the demand for bandwidth falling below the threshold, and data may be moved and/or rearranged within the memory device when the subset of memory elements is re-enabled. Altering the performance characteristic may increase a rate at which the memory device writes data.

Abstract: Systems and methods of determining a similarity between data units in a nonvolatile memory are disclosed. One method includes obtaining first and second data units and dividing the first and second data units into a first plurality of non-overlapping chunks of data and a second plurality of non-overlapping chunks of data. The method further includes determining a first plurality of values and a second plurality of values associated with the chunks, and determining a similarity between the first second data units based on the first plurality values and of the second plurality of values. In one example embodiment, a similarity between an incoming data unit and another data unit is determined based on the number of buckets storing an incoming index value and another index value associated with the another data unit. A plurality of buckets in a table is determined based on a selected plurality of hash values.

Abstract: A memory controller and method for scheduling commands in a memory controller are disclosed. A programmable solid state drive (SSD) controller and a non-volatile memory apparatus are provided. Data structures, termed “Superbufs” are utilized for organizing internal activities in the SSD controller. Each data structure can comprise a host command area, a command area, and a notes or scratch pad area. A memory controller can be configured to, upon receiving a host command, copy the original received host command into the host command area of a first data structure, generate a first command group, copy the first command group into the command area, and execute commands of the first command group. A data structure can be initialized to an idle state, and can transition to other states such as a new command received state, a read for execution state, a command group complete state and an error state.

Abstract: A system is provided for transforming an in-use RAID array from a first array configuration having a first parameter to a second array configuration having a second parameter while preserving a logical data structure of the RAID array. The system includes an extent reservation component, and a data migration component for reading unmigrated data from an area of an array arranged according to the first array configuration and writing the data to an area of the array arranged according to the second array configuration using reserved extents to store migrated data. The system also includes a first I/O component for performing I/O according to the first array configuration on unmigrated data prior to its reading by the data migration component, and a second I/O component for performing I/O according to the second array configuration on the migrated data after writing the migrated data.

Abstract: A method, apparatus, and computer program product are provided in a data processing system for performing a logical partition migration utilizing multiple mover service partition pairs. Responsive to a virtual machine monitor initiating a logical partition migration operation to move a logical partition from a source system to a destination system, a plurality of input/output paths are established between a plurality of mover service partition pairs. The virtual machine monitor performs the logical partition migration operation using the plurality of mover service partition pairs to transfer a memory image of the logical partition from the source system to the destination system to effect the logical partition migration operation. Responsive to failure of one of the plurality of input/output paths, the virtual machine monitor may complete the logical partition migration operation using at least one remaining mover service partition pair.

Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.

Abstract: An electronic device includes a semiconductor device, wherein the semiconductor device includes: a word line driving unit for driving a plurality of word lines; a first cell array arranged at one side of the word line driving unit; a second cell array arranged at the other side of the word line driving unit; a bias voltage generation unit, arranged between the first cell array and the second cell array, for generating a bias voltage based on currents flowing through the first reference resistance element included in the first cell array and the second reference resistance element included in the second cell array; a first read control unit; and a second read control unit.

Abstract: A solid state memory unit and method for protecting a solid state memory having a microprocessor are disclosed. The method may include receiving user-input requests for access to blocks of the solid state memory, the blocks of the solid state memory storing ordered virtual files. The user-input requests may have a respective sequence of virtual file position values. The method may include comparing the sequence of virtual file position values with a predetermined sequence of virtual file position values to verify the user-input requests, and when the sequence of virtual file position values equals the predetermined sequence of virtual file position values, responding to, via the microprocessor, requests for access to the blocks of the solid state memory to decrypt and transfer requested files stored. The predetermined sequence may correspond to a predetermined sequence of requests for access to files that can be selected by the user.

Abstract: A computing device includes a primary content storage machine configured to selectively store one or more content portions of a digital content item, such as game portions of a video game. The computing device is configured to determine a size of a dynamically changing content access window including one or more content portions usable to provide an above-threshold user experience, such as uninterrupted game play, based on a current access position of the digital content item or video game and historical user-specific play patterns or game play consumption rates of different users. The computing device is configured to dynamically load the primary content storage machine with the content portions or game portions corresponding to the content access window and dynamically unload the content or game portions outside of the content access window from the primary content storage machine.

Abstract: A cache memory is shared by N cores of a processor. The cache memory includes a unified tag part and a sliced data part partitioned into N data slices. Each data slice of the N data slices is physically local to a respective one of the N cores and physically remote from the other N-1 cores. For each core, the cache memory biases allocations caused by the core towards a physically local slice of the core. The cache memory may be arranged as a set-associative cache memory, and allocations may be based on a miss rate of a data slice and a number of M ways allocated to a core. A dispatch queue dispatches requests in a schedule fashion so that only one of the N data slices at a time returns data to each core.

Abstract: Methods and apparatus are provided for collecting cell-level statistics for detection and decoding in flash memories. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in a page of the flash memory device; and generating cell-level statistics for the flash memory device based on a probability that a data pattern was read from the plurality of bits given that a particular pattern was written to the plurality of bits. The cell-level statistics are optionally generated substantially simultaneously with a reading of the read values, for example, as part of a read scrub process. The cell-level statistics can be used to convert the read values for the plurality of bits to a reliability value for a bit among the plurality of bits.

Abstract: A disk drive includes a controller and at least one disk, which may include a first I-region, a second I-region, and an E-region. The first and second I-region may have a first final logical block address (LBA) and a second final LBA, respectively. The controller may be configured to cause information to be written to the first I-region and the second I-region using a first type and a second type of magnetic recording, respectively. The controller also may be configured to set at least one of the first final LBA or the second final LBA to a final LBA value higher than the at least one of the first final LBA or the second final LBA, respectively, after writing user data to at least a portion of the first I-region or the second I-region and without removing the user data.

Abstract: An administrator provisions a virtual disk in a remote storage platform and defines policies for that virtual disk. A virtual machine writes to and reads from the storage platform using any storage protocol. Virtual disk data within a failed storage pool is migrated to different storage pools while still respecting the policies of each virtual disk. Snapshot and revert commands are given for a virtual disk at a particular point in time and overhead is minimal. A virtual disk is cloned utilizing snapshot information and no data need be copied. Any number of Zookeeper clusters are executing in a coordinated fashion within the storage platform, thus increasing overall throughput. A timestamp is generated that guarantees a monotonically increasing counter, even upon a crash of a virtual machine. Any virtual disk has a “hybrid cloud aware” policy in which one replica of the virtual disk is stored in a public cloud.

Abstract: A data processing system 2 includes a cache hierarchy having a plurality of local cache memories and a shared cache memory 18. State data 30, 32 stored within the shared cache memory 18 on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.

Abstract: A nonvolatile memory is organized into blocks as erase units and physical pages as read/write units. A host addresses data by logical pages, which are storable in corresponding physical pages. Groups of logical pages may be further aggregated into logical groups as addressing units. The memory writes host data in either first or second write streams, writing to respective blocks either logical-group by logical-group or logical-page by logical-page in order to reduce the size of logical-to-physical-address maps that are cached in a controller random-access memory (RAM). A group-level map may be used to track logical groups. A page-level map may be used to track logical pages. Only one block at a time needs be open in the second stream to accept logical pages from multiple logical groups that are active. Garbage collection is performed on the blocks from each write stream independently without data copying between the two streams.

Abstract: A multi-layer memory and method for operation is disclosed. The memory includes multiple layers, where each layer includes flash memory cells having a greater bit per cell capacity than the prior layer and each layer may include a plurality of partitions having blocks exclusively associated with a particular data type. The method may include directing host data directly into a particular partition of a particular layer of the multi-layer memory upon receipt depending on a type of the data. The method may also include copying data within the same partition in a respective layer in a data relocation operation to generate more free blocks of memory so that data preferably stays within each layer and in the same partition, as well as transferring data from one layer to the next higher bit per cell layer within a same partition when layer transfer criteria are met.

Abstract: A memory protection circuit includes a memory access information register that stores memory access information related to memory areas which can be accessed by respective virtual machines, and an access determination circuit that determines whether to allow the virtual machines to access the memory areas based on a memory address when each of the virtual machines accesses a memory, information related to the virtual machines that access the memory, and the memory access information stored in the memory access information register. The memory access information register may comprise memory area setting registers and memory area allocation registers. A register access information register may indicate register areas which can be accessed by the virtual machines. A virtual machine scheduler or thread scheduler may determine an order of instructions to be executed.

Abstract: A data storage system, method and computer program product for managing copy on first write data for snapshot purposes are disclosed. In one embodiment, a determination is made whether new data is a first update of original data in a first section of a data storage device in response to receiving a write instruction to write the new data. The new data is provided to a first location of a cache memory and the original data to a second location of the cache memory. Providing the new data to the first location in the cache memory is not dependent on whether the original data has been copied from the data storage device. Further, the original data can be provided to the second location of the cache memory after new data is provided to first location of the cache memory. Completion of the write instruction is confirmed in response to providing the new data to the first location of the cache memory.

Abstract: A multidimensional storage array includes independently addressable storage elements and an input shifter. The storage elements are physically arranged into rows and columns and store particular bit(s) of a data word. The input shifter implements a circular shift to serially loaded data words to the multidimensional storage array. An output shifter may reverse the circular shift of a requested data word. The data entering the storage array may be shifted to expose column addressed data such that an entire column or columns may be fed to a requesting device in a single hardware clock cycle and/or may be shifted to expose row addressed data such that an entire row or rows may be fed to the requesting device in a single hardware clock cycle. The data entering the storage array may be shifted such that column addressed data words may be stored in a plurality of diagonally arranged storage elements.

Abstract: A data storage device with a FLASH memory accessed via multiple channels and a FLASH memory control method are disclosed. The control method includes dividing a plurality of blocks of a FLASH memory into groups to be accessed by a plurality of channels separately, each block comprising a plurality of pages; allocating a random access memory to provide a first set of cache spaces for the different ones of the plurality of channels; separating write data issued from a host to correspond to the plurality of channels; and after data arrangement in the first set of cache spaces for every channel is completed, writing data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels.