Patents Examined by Gopal C. Ray
  • Patent number: 7426593
    Abstract: In a transmitting terminal, a first displaying section displays, synchronously with a receiving terminal, a portion of content that has been transmitted to the receiving terminal. A second displaying section displays a portion of the content that has yet to be transmitted to the receiving terminal. A saving flag setting section sets a saving flag, the saving flag specifying whether to permit or prohibit the receiving terminal to save the content after the receiving terminal receives and displays the content. An adder adds the saving flag to the content; and a transmitter transmits the content to the receiving terminal with the saving flag.
    Type: Grant
    Filed: February 8, 2006
    Date of Patent: September 16, 2008
    Assignee: Sony Corporation
    Inventor: Nobuyoshi Tomita
  • Patent number: 7418527
    Abstract: The invention concerns a device in a communication network, the device comprising a component for obtaining a permanent identifier of the devices connected to the network and a component for establishing an association table between the permanent identifier of a device and a temporary identifier of the device in the network. The component for establishing the association table is adapted to read the permanent identifier of a device, the reading sequence of the permanent identifiers on the devices being based on a parameter pertaining to the device performing the reading. The invention also concerns a corresponding method.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: August 26, 2008
    Assignee: Thomson Licensing
    Inventors: Guillaume Bichot, Nicolas Burdin
  • Patent number: 7386647
    Abstract: A system and method is disclosed for the handling of interrupts by the disabled logical processors of an information handling system or computer system. An interrupt service routine is written to the read-only portion of system memory. Upon receipt of an interrupt, each disabled logical processor branches to the hard coded interrupt service routine. The interrupt service routine can be written to read only memory because the context, current instruction, and return state of the disabled logical processor are known, and the disabled logical processor will not need to write to system memory during the execution of the interrupt service routine. Following the handling of the interrupt by another logical processor of the computer system, each disabled logical processor returns to the halt state.
    Type: Grant
    Filed: October 14, 2005
    Date of Patent: June 10, 2008
    Assignee: Dell Products L.P.
    Inventors: Christopher H. McFarland, Juan F. Diaz
  • Patent number: 7386645
    Abstract: An electronic system comprises a defined number N of functional modules, including a defined number P of initiator modules and a defined number Q of target modules, where N, P and Q are integer numbers such that 2?P?N and 1?Q?N. In the event of a plurality of conflicting requests to access a common resource originating from a plurality of respective initiator modules, an arbitration unit grants an exclusive right of access to the resource to a defined one of these initiator modules. The arbitration unit is constructed either to apply a standard arbitration mechanism to these respective initiators, or to apply as a priority a specific arbitration mechanism only to the members of a subset of these initiator modules, for each of which it receives a linked privileged access signal.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: June 10, 2008
    Assignee: STMicroelectronics SA
    Inventors: Herve Chalopin, Laurent Tabaries
  • Patent number: 7380037
    Abstract: A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: May 27, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Yoshihiro Tabira
  • Patent number: 7373447
    Abstract: A multi-port processor architecture having a first bus, a second bus and a central processing unit. The central processing unit having a first and second ports coupled to first and second busses respectively. A first bus to second bus bi-directional interface couples the first bus to the second bus. Optionally, the first bus or the second bus can be connected to a memory. The architecture can include a third bus with a third bus to first bus bi-directional interface connecting the third bus to the first bus and a third bus to second bus bi-directional interface connecting the third bus to the second bus. If there are additional bus systems, the Nth port (where N is an integer greater than 2) is connected to the Nth port. The buses use bi-directional interfaces to communicate with each other without using CPU or memory resources, reducing memory access latency.
    Type: Grant
    Filed: November 9, 2004
    Date of Patent: May 13, 2008
    Assignee: Toshiba America Electronic Components, Inc.
    Inventor: Lutz Gerhard Eduard Filor
  • Patent number: 7373443
    Abstract: Provided is a method for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7373442
    Abstract: Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: May 13, 2008
    Assignee: Intel Corporation
    Inventor: Pak-Lung Seto
  • Patent number: 7370130
    Abstract: A core logic device of a computer system includes a programmable interrupt controller (PIC), an input/output advanced programmable interrupt controller (I/O APIC) and a virtual wire unit. The PIC outputs a control signal to the virtual wire unit via an interrupt pin in response to an external interrupt signal asserted by a peripheral device before an operating system is loaded in the computer system. The virtual wire unit outputs an interrupt control packet to the CPU in response to the control signal wherein the interrupt vector contents carried by the interrupt control packet are ignored by the CPU. After the operating system is loaded in the computer system, the I/O APIC outputs another interrupt control packet to the CPU in response to the external interrupt signal.
    Type: Grant
    Filed: April 20, 2006
    Date of Patent: May 6, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Ming-Wei Hsu, Wayne Huang
  • Patent number: 7370134
    Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: May 6, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 7356630
    Abstract: A processor control device includes a processor executing an instruction, a module coupled to the processor through a bus and processing independently from the processor, the module is provided in a plural number and a polling processing unit coupled to each module, the polling processing unit stopping an operation of the processor depending on an execution status of the module processing at a time of an access request from the processor.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: April 8, 2008
    Assignee: Seiko Epson Corporation
    Inventors: Shoji Hoshina, Masakazu Isomura, Akinari Todoroki
  • Patent number: 7356638
    Abstract: A system provides communication between components of a computer data storage system using out-of-band (OOB) signaling. The system includes a plurality of data storage devices having a local controller for directing data flow to each of the plurality of data storage devices. A switch is coupled to the local controller to direct data to the set of the plurality of data storage devices. First and second initiators are coupled to the switch. The first initiator communicates the OOB signals through the switch alternatively to the local controller or to the second initiator.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: April 8, 2008
    Assignee: International Business Machines Corporation
    Inventors: William G. Holland, Shah Mohammad Rezaul Islam, Greg S. Lucas, Yoshihiko Terashita
  • Patent number: 7353316
    Abstract: A plurality of memory modules used in a computer system each include a memory hub that is connected to a plurality of memory devices. The memory modules are connected to each other in series so that signals are coupled between the memory modules and the memory hub controller through any intervening memory modules. The signals are coupled to and from the memory modules through high-speed bit-lanes. In the a bit-lane connected to any of the memory hubs is inoperative, the memory hub re-routes signals that would be coupled through the inoperative bit-lane to an adjacent bit lane. When the signal reaches a memory hub in which the bit-lane is no longer inoperative, the memory hub routes the signal back to the original bit lane. In this manner, multiple bit-lane failures can be accommodated using a signal extra bit-lane.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: April 1, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Michael Erdmann
  • Patent number: 7353307
    Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: April 1, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Rakesh N. Joshi, Mark S. Gary, Kenneth L. Williams
  • Patent number: 7350013
    Abstract: A programmable logic device (PLD) includes programmable logic circuitry and a bridge circuitry. The bridge circuitry includes a first interface circuitry and a first signal select circuitry. The first signal select circuitry couples to the first interface circuitry and the programmable logic circuitry. The bridge circuitry further includes an information interchange circuitry. The first signal select circuitry is configured to selectably provide a communication path between the information interchange circuitry and either the programmable logic circuitry or the first interface circuitry.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: March 25, 2008
    Assignee: Altera Corporation
    Inventor: Andrew Crosland
  • Patent number: 7350010
    Abstract: Embodiments of the present invention pertain to methods and systems are described for switching root cells for a computer system without requiring the computer system to be re-booted. In one embodiment, objects are used to represent fixed registers associated with a first cell and a second cell of the computer system. In response to detecting that the second cell should be used instead of the first cell as a root cell for the computer system, the objects are used to communicate information between firmware and an operating system associated with the computer system, wherein the information describes the fixed registers associated with the second cell.
    Type: Grant
    Filed: October 28, 2005
    Date of Patent: March 25, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dong Wei, Raghuram Kota, Toshimitsu Kani
  • Patent number: 7343439
    Abstract: The functionality provided to electronic devices by application specific removable modules is enhanced by viewing the removable modules as first-level removable modules and providing them with at least one second-level removable slot for selectively nesting second-level removable modules having particular external I/O capabilities. The functionality provided to the electronic devices by such a first-level removable module can thus be provided in part by the application specific circuitry within the removable module and further in part by the type of external I/O of the second-level removable module.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: March 11, 2008
    Assignee: Socket Communications, Inc.
    Inventors: Kevin J. Mills, Michael L. Gifford
  • Patent number: 7337258
    Abstract: Devices are assigned to different buses at development time as well as dynamically during operation, based on actual performance. At development time, bus assignment can be determined based on experiments and direct observation of how devices behave in various configurations. At run time, load on each bus is preferably measured periodically, and when it is uneven, devices are reallocated to different buses. In an alternative embodiment, a user can specify a preference for using more or fewer buses in order to optimize operation for efficiency or lower power consumption.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: February 26, 2008
    Assignee: Apple Inc.
    Inventors: Robert L Bailey, Brian D Howard, Lesley B Wynne
  • Patent number: 7337261
    Abstract: An integrated semiconductor memory device for use within an integrated USB memory apparatus has a controller, a flash memory in communication with the controller, a USB interface circuit in communication with the memory controller, and an integrated circuit package for maintaining at least one of the controller, the flash memory, and the USB interface within the physical dimensions of a USB connector of the USB memory apparatus.
    Type: Grant
    Filed: April 13, 2006
    Date of Patent: February 26, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Sukegawa, Azusa Kanayama, Hiroyuki Kamei
  • Patent number: 7337249
    Abstract: A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (for cascading).
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: February 26, 2008
    Assignee: Pact XPP Technologies AG
    Inventors: Martin Vorbach, Robert M√ľnch