Abstract: A PCI-Express compatible switch is provided with two or more, internal virtual buses. In one embodiment, at least one of the plural virtual buses is designated as a special bus that is limited to having no more than 16 devices on it even though the protocol allows for more. In a supplemental or alternate embodiment, at least one virtual bus is limited to having no devices on it. A non-transparent bridge is provided on at least one of the special buses for providing cross-border routing of packets from one root domain to another root domain. The number-of-devices limitation placed on the special bus reduces the number of bits needed in a corresponding Device identifying field of a destination ID Tag to 4 or less, this integer number being smaller than the prescribed 5 bits called for by the PCI-Express standard for addressing the maximum of 32 devices per bus.

Abstract: A method is provided for on-demand communications in a communication network with support for a plurality of communication units participating in a common communication, which includes multiple signal initiators, each supplying a signal, which are virtually simultaneously conveyed as part of the common communication. At least one example of an on-demand communication includes push to talk. Additionally, a signal initiator is provided, which is adapted to support on-demand communications in a multi-signal initiator environment.

Abstract: An optical disc drive that includes a driving unit including a spindle motor to rotate an optical disc, an optical pickup to access the optical disc, and a connection board connected to a computer. A control board to control the driving unit, is installed at an interface device of the computer, separate from the driving unit, and is connected to the connection board.

Abstract: Systems and methods for coordinating the interoperability of devices with varying capabilities are disclosed. A host device may inquire as to the capabilities of a storage device in a storage network. A routing device may receive this response, and if the routing device has a higher capability than the storage device the routing device may convert the response to a response that reflects the higher capabilities of the routing device before sending the response on to the host. However, if the storage device has a higher capability than the routing device, the routing device may pass the response through to the host unaltered so the host may take advantage of the capabilities of the storage device. Alternatively, the router may convert the response to a response that reflects the lower capabilities of the routing device before sending the response on to the host.

Abstract: A system includes a core chipset that is configured to communicate with a central processing unit. The system includes a memory bridge configured to communicate with memory. An accelerated graphics processor configured to communicate with a graphics device. An input/output bridge communicates with the memory bridge and the accelerated graphics processor and includes a bus controller. A Peripheral Component Interconnect-Extended (PCI-X) bus communicates with the bus controller. An integrated circuit includes a bus interface that communicates with the PCI-X bus. An Ethernet controller communicates with the bus interface. A serial advanced technology attachment (ATA) host adapter communicates with the bus interface and is configured to control a mass data storage unit.

Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

Abstract: The present invention is generally directed to various methods and systems for dynamically controlling metrology work in progress. In one illustrative embodiment, the method comprises providing a metrology control unit that is adapted to control metrology work flow to at least one metrology tool, identifying a plurality of wafer lots that are in a metrology queue wherein the wafer lots are intended to be processed in at least one metrology tool, and wherein the metrology control unit selects at least one of the wafer lots for metrology processing in the at least one metrology tool and selects at least one other of the plurality of wafer lots to be removed from the metrology queue based upon the metrology processing of the selected at least one wafer lot in the at least one metrology tool.

Abstract: A data port operates to support symmetric PCI Express-type data transfers when in a first mode of operation. When in a second mode of operation, at least a portion of the data port connections are used to support an asymmetric PCI Express-type data transfer. The asymmetric data transfer is accommodated by supporting, with respect to the asymmetric data port, partial data lanes, thereby reducing the number of data channels implemented in a direction of the lower data rate transfer.

Abstract: An apparatus for arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The apparatus provides arbitration logic with an indication as to whether the ready signal from a storage element has been asserted, and employs the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: Provided are techniques for determining a timer value. An advised number of packets per interrupt for both receive and transmit directions of traffic is determined. Current timer values for both receive and transmit directions of traffic are adjusted based on the determined advised numbers of packets per interrupt. A new timer value to be used for both receive and transmit directions of traffic is calculated. Other embodiments are described and claimed.

Abstract: Methods and systems, including computer program products, implementing techniques for receiving, at a first device of a switched fabric network, requests from one or more applications, each request being destined for a second device of the network, the first device being connected to the second device by a virtual channel; generating, for each request, a descriptor comprising a traffic class designation; and adding the descriptor to an ordered list of descriptors, the descriptor having a location in the ordered list that is based on the traffic class designation of the descriptor.

Abstract: A redundant external storage virtualization computer system. The redundant storage virtualization computer system includes a host entity for issuing an IO request, a redundant external storage virtualization controller pair coupled to the host entity for performing an IO operation in response to the IO request issued by the host entity, and a plurality of physical storage devices for providing storage to the computer system. Each of the physical storage devices is coupled to the redundant storage virtualization controller pair through a point-to-point serial signal interconnect. The redundant storage virtualization controller pair includes a first and a second storage virtualization controller both coupled to the host entity. In the redundant storage virtualization controller pair, when the second storage virtualization controller is not on line, the first storage virtualization controller will take over the functionality originally performed by the second storage virtualization controller.

Abstract: A high assurance processing system includes a plurality of data processors coupled in parallel, a bridge coupled to the plurality of data processors, and an input/output processor coupled to the bridge for coupling to a sensor and an effector. Sensor data passes to the bridge through the input/output processor for processing by the parallel data processors, which generate redundant effector data for comparison by the bridge to detect errors. If data matches are found, data is transmitted to the effector.

Abstract: A bus monitor is provided as a tool for developing, debugging and testing a system having an embedded processor. The bus monitor resides within the same chip or module as the processor, which allows connection to internal processor buses not accessible from external contacts. The monitor uses a separate circular buffer to continuously store, in real-time, data traces from each of one or more internal processor buses. Upon the occurrence of a trigger condition, storage stops and a trace is preserved. Trigger conditions can depend on events occurring on multiple buses and are downloaded via an interface from an external device. Data traces are uploaded via the interface to an external device for evaluation of processor operation.

Abstract: An improved method for accessing data is disclosed, which is capable of increasing the efficiency of data access by reducing the time consumed by registering data in the system memory while transferring data between computer peripherals.

Abstract: In various embodiments, an apparatus comprises a plurality of agents and an interconnect. In one embodiment, the plurality of agents includes first through fourth agents. The interconnect comprises a plurality of segments that are switchable (e.g. using a plurality of selection circuits) to form communication paths between the agents, and a first segment is included in a first communication path from the first agent to the second agent, and is also included in a second communication path from the third agent to the fourth agent. In another embodiment, each segment is driven by a selection circuit. At least one selection circuit has at least one segment and an output from at least one agent as inputs. In yet another embodiment, an arbiter is configured to determine a communication path on the interconnect for each requesting agent to the destination agent over the segments.

Abstract: A data transfer control device including: a link controller which analyzes a received packet transferred from a host-side data transfer control device through a serial bus; an interface circuit which generates interface signals and outputs the generated interface signals to an interface bus; and an internal register in which is set interface information for specifying signal types of the interface signals output from the interface circuit. The interface circuit includes first to Nth interface circuits (N is an integer greater than one), and each of the first to Nth interface circuits generates an interface signal of a signal type according to the interface information set in the internal register.

Abstract: A bus system for handling changes in an access address range of a subject-of-access or a bus master is disclosed. The bus system can have an address monitor unit including a table which is shared among a plurality of bus masters and stores therein access right information. By referencing the table, the presence or absence of an access right for each of the bus masters can be determined. The table may be rewritten as appropriate to handle address range changes.

Abstract: In a wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are first attempted before asynchronous transfers, as long as the periodic transfers are successful. When failures are occurring, the hardware includes a mechanism having a software-configurable threshold specifying the number of errors a given endpoint can tolerate before it is paused in the schedule. By pausing transfer attempts that are likely to again fail, endpoints with successful transfers are favored over those experiencing errors. When the number of active transfers pending exceeds a software-configurable notification threshold for isochronous endpoints, the hardware notifies the software of this state, corresponding to a low-buffer condition at the receiver.

Abstract: An apparatus for distributing power in a computer system includes a power supply device; a processing device including a CPU module and a plurality of I/O modules; and an insert line coupled between the power supply and the processing device. The insert line is connected to each of the CPU module and the plurality of I/O modules before terminating at a ground connection within the processing device. The CPU module and the plurality of I/O modules are powered by the power supply. When one of the CPU module and the plurality of I/O modules is removed from the processing device, the power supply senses that the insert line is no longer grounded, and removes power from the CPU module and the plurality of I/O modules.