Abstract: The present invention relates to a method and arrangement for controlling dataflow on a databus, especially for avoiding reception problems by a receiver unit. The databus connects at least one receiver unit to one or several transmitter units. The method comprises the steps of transmitting by the receiver unit on the databus a control data sequence to be received by the transmitting units, which alter transmission mode.

Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from a second type of device that uses a second cache-line size, such that communications between the first type of devices are enabled over a plurality of first routes, such that communications between the second type of devices are enabled over a plurality of second routes, and such that communications between the first type of devices and the second type of devices are disabled.

Abstract: A method of notifying clients of a change in a USB including a first client requesting notification of a first change in the USB, detecting the first change in the USB, and notifying the first client requesting notification that the first change in the USB occurred.

Abstract: A shared-IRQ user-defined interrupt signal handling method and system is proposed, which is designed for use with a computer platform to allow a group of peripheral devices connected to an interrupt-configurable peripheral interface to share system interrupt lines IRQ with another group of peripheral devices connected to an interrupt nonconfigurable peripheral interface; which is characterized by the provision of an interrupt configuration table for defining a virtual device for the interrupt-configurable peripheral interface as well as each specific system interrupt line that is shared by the two groups of peripheral devices. This feature allows system interrupt lines IRQ to be shared by the two different groups of peripheral devices, and also allows the implementation to be easier to carried out than prior art without involving complex and difficult BIOS coding.

Abstract: A method for configuring a communication port of a communications interface of an information handling system into a plurality of virtual ports. A first command is issued to obtain information indicating a number of images of virtual ports supportable by the communications interface. A second command is then issued requesting the communications interface to virtualize the communication port. In response to the second command, one or more virtual switches are then configured to connect to the communication port, each virtual switch including a plurality of virtual ports, such that the one or more virtual switches are configured in a manner sufficient to support the number of images of virtual ports indicated by the obtained information. Thereafter, upon request via issuance of a third command, a logical link is established between one of the virtual ports of one of the virtual switches and a communicating element of the information handling system.

Abstract: Provided are techniques for interrupt processing. An Input/Output device determines that an event has occurred. The Input/Output device determines a processor identifier and determines an event data structure identifier for an event data structure into which data for the event is stored using the processor identifier. The Input/Output device also determines a vector identifier for an interrupt message vector into which an interrupt message for the event is written. Then, interrupt message data is written to the interrupt message vector to generate an interrupt.

Abstract: A method is described which comprises propagating electronic signals within circuitry comprising a transmitter to select a number of the transmitter's lanes, set a speed for each of the lanes, and set at least a driver supply voltage for each of the lanes. The number and speed determine the transmitter's bandwidth. Power consumed by the transmitter as a consequence of the lane number selection, lane speed setting and driver supply voltage is less than a power that would have been consumed by the transmitter had another available combination of lane number, lane speed and supply voltage been effected for the transmitter.

Abstract: Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host controller has a reduced set of pins for handling communication in a plurality of communication protocols. The total number of pins needed for driving communication in a plurality of communication protocols is reduced by sharing at least one control pin or at least one data pin or combination thereof between at least some of the plurality of communication protocols. In one embodiment, data communications in different protocols overlapping in time can be interleaved onto to a shared data path by suspending a current transmission until a later higher priority transmission is complete.

Abstract: Described herein are methods and systems for conducting computer system communications with a number of different devices that communicate with the computer system in a number of different protocols via a protocol-shared combination host controller. Combination host controller has a reduced set of pins for handling communication in a plurality of communication protocols. The total number of pins needed for driving communication in a plurality of communication protocols is reduced by sharing at least one control pin or at least one data pin or combination thereof between at least some of the plurality of communication protocols. In one embodiment, data communications in different protocols overlapping in time can be interleaved onto to a shared data path by suspending a current transmission until a later higher priority transmission is complete.

Abstract: A method and apparatus for presenting a plurality of link devices as separate nodes within a single serial bus module by generating individual or a distinct configuration ROM image for each link device in the module. Each configuration ROM includes an entry for a distinct identifier representing the corresponding link device thereby creating a one to one mapping of link device to node via the distinct configuration ROM.

Abstract: An apparatus having a first plurality of I/O ports, a second I/O port, and core logic. The first plurality of I/O ports is coupled to a plurality of operating system domains (OSDs) through a load-store fabric, each routing transactions between the plurality of OSDs and the switching apparatus. The second I/O port is coupled to a first shared input/output endpoint. The first shared input/output endpoint requests/completes the transactions for each of the plurality of OSDs. The core logic is coupled to the first plurality of I/O ports and the second I/O port. The core logic routes the transactions between the first plurality of I/O ports and the second I/O port. The core logic designates a corresponding one of the plurality of OSDs according to a variant of a protocol, where the protocol provides for routing of the transactions only for a single OSD.

Abstract: A method and an apparatus to efficiently handle read completions that satisfy a read request are presented. The apparatus comprises a first port to receive data that partially satisfies a read request, a second port, wherein the data is forwarded via the second port if the second port is idle, a buffer to store the data if the second port is busy, and a combiner to combine the stored data with additional data that partially satisfies the read request as the additional data is received via the first port, wherein the second port forwards the combined data when the second port is not busy.

Abstract: A method and an engineering system that reduce the configuration complexity with regard to a possible expansion of the automation device are provided. The automation device includes slave units and a master unit (7, 15) connected to the slave units via a bus. The slave units include one or more slave units (11, 12, 16, 17) and one or more reserve slave units (13, 18). The configuration of a reserve slave unit (13, 18) enables the master access time interval (20) and the slave access time intervals (21, 22, 23) to be expanded for a possible expansion of the automation device. As a result, a configured automation device of this type can be expanded by an additional slave unit without additional configuration or reconfiguration.

Abstract: There is disclosed a bus interface unit for transferring machine specific register (MSR) requests between a plurality of bus devices. The bus interface unit comprises: 1) a plurality of input ports for receiving incoming MSR requests from the plurality of bus devices; 2) a plurality of output ports for transmitting data to the plurality of bus devices; and 3) a controller for reading N routing associated with a first received MSR request and comparing a first identification (ID) value in a predetermined M-bit field in the N routing bits to a first designated value. The controller, in response to a determination that the first ID value does not equal the first designated value: 1) realigns the N routing bits such that remaining ones of the N-M bits outside the predetermined M-bit field are moved into the predetermined M-bit field and 2) transmits the realigned N routing bits via a first one of the plurality of output ports identified by the first ID value.

Abstract: Methods and apparatuses are described for improving information transfer over a universal serial bus (USB). In some embodiments, an apparatus includes a USB-compliant near-end link and control logic coupled with the USB-compliant near-end link. The control logic may translate a USB-compliant reflective signal received from a USB host to a terminated signal. Other embodiments are described and claimed.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.

Abstract: The invention relates to universal serial bus circuits utilized in USB devices and USB hubs. Specifically, the invention relates to circuitry used to detect whether the hub or device is connected to a USB host, i.e. to detect connection status of the device or hub. The present invention provides a USB circuit comprising a microprocessor which receives signaling concerning the connection status of the USB circuit to a USB host circuit, first and second data signal lines which transmit respective first and second data signals to the microprocessor, a USB host power supply signal line which receives USB host power signaling to indicate connection status, and wherein the USB circuit analyzes the USB power supply signal line and change the data signal transmittal down the first and second data lines according to the connection status of USB circuit to the USB host circuit.

Abstract: A method enabling I/O devices to be shared among multiple operating system domains, including first communicating with each of the operating system domains according to a protocol that provides exclusively for a single system domain ithin the load-store fabric; and second communicating with the shared I/O endpoint according to a variant of the protocol to enable the shared I/O endpoint to associate a prescribed operation with a corresponding one of the independent operating system domains. The second communicating includes encapsulating an OS domain header within a transaction layer packet that otherwise comports with the protocol, wherein the value of the OS domain header designates the corresponding one of the operating system domains; and via core logic within a swithching apparatus, mapping the independent operating system domains to the shared I/O endpoint.