Abstract: A system memory includes a memory hub controller, a memory module accessible by the memory hub controller, and an expansion module having a processor circuit coupled to the memory module and also having access to the memory module. The memory hub controller is coupled to the memory hub through a first portion of a memory bus on which the memory requests from the memory hub controller and memory responses from the memory hub are coupled. A second portion of the memory bus couples the memory hub to the processor circuit and is used to couple memory requests from the processor circuit and memory responses provided by the memory hub to the processor circuit.

Abstract: An arbiter in a bus system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.

Abstract: In one embodiment, a processing node includes a plurality of processor cores and a reconfigurable interconnect. The processing node also includes a controller configured to schedule transactions received from each processor core. The interconnect may be coupled to convey between a first processor core and the controller, transactions that each include a first corresponding indicator that indicates the source of the transaction. The interconnect may also be coupled to convey transactions between a second processor core and the controller, transactions that each include a second corresponding indicator that indicates the source of the transaction. When operating in a first mode, the interconnect is configurable to cause the first indicator to indicate that the corresponding transactions were conveyed from the second processor core and to cause the second indicator to indicate that the corresponding transactions were conveyed from the first processor core.

Abstract: A computer system associated with a plurality of interrupt sources that produce interrupt signals may include interrupt signal processing blocks corresponding to the interrupt sources, respectively. Each of the interrupt processing blocks can include: a counter for generating an interrupt count value associated with the number of interrupt signals received from the corresponding interrupt source; a first register for storing the interrupt count value; a logic circuit for to generate an interrupt request signal according to the interrupt count value; and a second register for storing a service routine address associated with the interrupt source.

Abstract: A control hub includes a first interface and a second interface to transfer data. The first interface connects to a first bus. The second interface connects to a peripheral bus. The control hub receives configuration address and configuration data during a configuration access. The control hub transfers the configuration data between the first interface and the second interface without transferring the configuration data to a configuration data register. The control hub further includes other interfaces to allow access to peripheral devices for system management and testing purposes.

Abstract: Provided is a system for interfacing with storage units, including a backplane, at least one slot in the storage enclosure for receiving one storage unit, and two physical interfaces on the backplane for at least one slot. The storage unit is capable of being positioned in the slot to mate with one of the two physical interfaces for the slot, wherein each physical interface supports different storage interconnect architectures.

Abstract: A polling method, apparatus, and system to detect the attachment and detachment of Universal Serial Bus devices in a wireless system. A hub provides a wired connection to the host and wireless attachment points for its devices, The host periodically queries the hub for changes in the hub's status register by sending a polling message through each of its wireless ports, and awaits a response. A peripheral device that wishes to attach to the system responds by sending its unique peripheral address. If a device currently occupies the port, the hub sends out the device's unique address in the polling message. If the device is still present, it responds by sending its unique peripheral address. If a response is not received after multiple retries, the device is considered detached. The hub thus determines the status of the ports and updates the status register, which is queried by the host.

Abstract: In wireless USB data transfers over UWB, software configures hardware thresholds to control data transfer in a manner that uses bandwidth for good connections over bad connections, given the high error rate experienced with wireless USB. Periodic transfers are first attempted before asynchronous transfers, as long as the periodic transfers are successful. When failures are occurring, the hardware includes a mechanism having a software-configurable threshold specifying the number of errors a given endpoint can tolerate before it is paused in the schedule. By pausing transfer attempts that are likely to again fail, endpoints with successful transfers are favored over those experiencing errors. When the number of active transfers pending exceeds a software-configurable notification threshold for isochronous endpoints, the hardware notifies the software of this state, corresponding to a low-buffer condition at the receiver.

Abstract: An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transistor connected in parallel with a tri-state buffer. The pass transistors and tri-state buffers are controlled by configuration SRAM bits. Some of the pass-through interconnect conductors are connected by programmable elements to the address, data and control signal lines of the SRAM blocks, while other pass through the SRAM blocks with out being further connected to the SRAM bussing architecture.

Abstract: The present invention, a multiprocessor chip pervasive command interface, collects different types of pervasive commands into individual queues for each command type. As permitted by various grouping rules, valid commands are grouped together into one single command and placed on a functional interchip communications bus. This grouping of commands maximizes pervasive command bandwidth while the use of the functional bus minimizes the number of interchip connections.

Abstract: A system and method for configuring expandable buses wherein a host supports a plurality of expandable buses are provided. A plurality of devices are arranged to form a plurality of groups. Each group forms a chain of devices on an expandable bus. Each chain includes an input connector. The chains are configured such that connecting an expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to that particular expandable bus of the host. The absence of connecting any expandable bus of the host to the input connector for a particular chain causes that particular chain to be directly connected to a different chain so as to be indirectly connected to one of the expandable buses of the host. In another embodiment, the connections to an expandible bus of the host must be consistent with a predetermined connection logic.

Abstract: A method and apparatus for supporting heterogeneous agents in on-chip busses. In one embodiment, the method includes the detection of a bus arbitration event between at least a first bus agent and a second bus agent. In one embodiment, a bus arbitration event is detected when at least the first bus agent and the second bus agent assert their respective bus request signals in a single clock cycle. Once a bus arbitration event is detected, bus ownership may be granted to both the first bus agent and the second bus agent, when the first bus agent and the second bus agent have different grant-to-valid latencies. In the embodiment, heterogeneous bus agents may coexist on a bus without requiring wasted or unused bus cycles following establishment of bus ownership. Other embodiments are described and claimed.

Abstract: A method of arbitration within a data processing apparatus between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit. The plurality of paths include a shared connection, the data processing apparatus having a plurality of initiator logic elements for initiating transfers and a plurality of recipient logic elements for receiving transfers, for each transfer the corresponding path coupling the initiator logic element responsible for initiating that transfer with the recipient logic element destined to receive that transfer. The method comprises the steps of providing to arbitration logic an indication as to whether the ready signal from a storage element has been asserted, and employing the arbitration logic to select, in dependence on predetermined criteria including at least that indication, one of the plurality of transfers for routing via the shared connection.

Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.

Abstract: At each node of the data transmission/reception system of the present invention on a bus of an IEEE 1394, the following operations are sequentially performed: necessary initialization at the time of bus resetting; and GUID acquisition, restoration of Broadcast-out connection, restoration of Broadcast-in connection, and restoration of Point-to-point connection according to a restoration connection queue registering an execution order of respective connection restoration operations if there is a PENDING status of each connection before a passage of a predetermined time, after the bus resetting. Moreover, the restoration of each connection is subdivided into a plurality of processing steps when necessary, and controlled to select a proper processing step.

Abstract: One embodiment of the invention includes a system for changing a bus configuration of a computing device. The system includes a first bus of the computing device, a second bus, and a third bus. Additionally, a multiplexing module is coupled with the first, second, and third buses. As such, the multiplexing module can selectively couple the first bus with the second bus or the third bus. A configuration module is coupled with the multiplexing module and controls its operation.

Abstract: A system interface having: a packet switching network; a cache memory; and a plurality of directors. One portion of such directors is adapted for coupling to a host computer/server and another portion of the directors is adapted for coupling to a bank of disk drives, the plurality of directors and cache memory being interconnected through the packet switching network. Each one of the directors is coupled to a crossbar switch. The cross bar switch is directly connected to at least two other ones of the cross bar switches networks and indirectly connected to of other ones of the crossbar switches through the at least two directly connected crossbar switches.

Abstract: A distributed interface between a microprocessor or a standard bus and user macro-cells belonging to an ASIC, FPGA, or similar silicon devices includes a main module connected to the microprocessor bus on one side and to a COMMON-BUS inside the interface on which a cluster of peripheral modules is appended on the other side. Peripheral modules are also connected to the user macro-cells through multiple point-to-point buses to transfer signals in two directions. A set of hardware and firmware resources such as registers, counters, synchronizers, dual port memories (e.g. RAM, FIFO) either synchronous or asynchronous with respect to macro-cells clock is encompassed in each peripheral module. Subsets of the standard resources are diversely configured in each peripheral module in accordance with specific needs of the user macro-cells.

Abstract: A computer accessory device—USB sharer includes a multiplexer, which is connected to a computer host, a human interface device (HID) chip, which is connected to one output end of the multiplexer, a device output end, which is connected to another output end of the multiplexer; and a busyness detection module, which is connected to the middle of the HID chip and the device output end. The USB sharer may reach a sharing function of “N to 1” by applying N?1 sets of “2 to 1” sharer, in which, at least one “2 to 1” sharer's output end is connected to the device output end and, for other N?2 sets of “2 to 1” sharer, of which at least one output end is connected to the input end of another “2 to 1” sharers.

Abstract: An USB composite device using hub link layer and UTMI interface is disclosed, which connects to a host through an USB cable. The device includes an USB physical layer, a hub link layer and plural functional link layers. The USB physical layer can receive and transmit USB signals. The hub link layer connects to the USB physical layer through an UTMI interface, has plural downlink ports to provide linking, and responds an USB transaction performed by the host. The plural functional link layers connect to the downlink ports of the hub link layer through plural UTMI interfaces.