Abstract: A system allows queuing interconnect transactions of a first transaction type and a second transaction type according to an interconnect protocol for a computer system in a transaction order queue (TOQ). The queuing technique imposes an additional ordering on interconnect transactions in addition to ordering rules of the interconnect protocol. Transactions can bypass the TOQ if no transactions of the first type are awaiting execution or are in the TOQ. Transactions are dequeued from the TOQ if no transactions of either the first transaction type or the second transaction type are awaiting scheduling for execution.

Abstract: Ownership of a peripheral bus between a peripheral device and a plurality of master devices is assigned to one of the master devices. Each master device has an associated controller for controlling the peripheral device via the peripheral bus. Communication occurs without impediment between the master device and its controller that have ownership of the bus, thereby conducting transactions via the peripheral bus and peripheral device. Communication with the master device and controller not having ownership is blocked, making the controller look busy to the master device and making the master device look idle to the controller. The ownership is assigned to the master/controller pairs using an arbiter arrangement.

Abstract: A network device for handling data and a method for handling data in a network device are disclosed. The network device includes at least one media port and at least one high speed docking station, communicating with the at least one media port. At least one master is provided in the network device, where the at least one master is connected to the at least one high speed docking station. The master is configured to handle and process data received by the at least one media port and passed to the master through the at least one high speed docking station. The network device is configured to handle media ports of different media types. Thus, the device can handle data received through different media ports that have different media types with the same master, making the network device easily configured to meet a customer's needs.

Abstract: A computer accessory device—USB share is comprised of a multiplexer, which is connected to a computer host; a human interface device (HID) chip, which is connected to one output end of the multiplexer; a device output end, which is connected to another output end of the multiplexer; and a busyness detection module, which is connected to the middle of the HID chip and the device output end. The USB sharer may reach a sharing function of “N to 1” by applying N?1 sets of “2 to 1” sharer. Wherein, at least one “2 to 1” sharer's output end is connected to the device output end and, for other N?2 sets of “2 to 1” sharer, of which at least one output end is connected to the input end of another “2 to 1” sharers.

Abstract: A method and system for system-management event detection, consolidation, reporting and storage is provided. The method and system may be used in a computer system for above-mentioned purposes. The method and system may be connected to central processing unit through a memory interface. The method and system comprises several system-management event sources that monitor system management events in the computer system. Each system-management-event source is connected to at least one system-management-event node that is in a communication connection with a system-management event-module. Each system-management-event node is operable to detect and transmit data about system-management events to the system-management-event module. The system-management-event module is able to report the occurrence of an event, is able to store data about system-management events and is operable to transmit data about system-management events to the central processing unit.

Abstract: An external memory engine selectable pipeline architecture provides external memory to a multi-thread packet processor which processes data packets using a multi-threaded pipelined machine wherein no instruction depends on a preceding instruction because each instruction in the pipeline is executed for a different thread. The route switch packet architecture transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator.

Abstract: A blade server system with integrated KVM switches is described. The blade server system has a chassis, a management board, a plurality of blade servers, and an output port. Each of the blade servers has a decoder and a switch. Each of the blade servers further has a select button and a processor. The decoder receives an encoded data from the management board and decodes the encoded data into command information when one of the blade servers is selected. The switch receives the command information and is switched according to the command information. The command information indicates which switch is to be turned on and which are to be turned off. The output port connects the peripheral devices for controlling the selected blade server. The management board may determine which blade server is to be selected by the button condition, commands from the peripheral devices or a request from a network computer.

Abstract: A protocol for facilitating access to a local input/output device of a remote node across a network. The local input/output device is configured according to a local communication technology (e.g., PCI—Peripheral Component Interconnect), but is accessed remotely (e.g., across a set of InfiniBand (IB) communication links). A host server or other computer (e.g., an InfiniBand host) includes a channel adapter and a nexus driver for conveying or retrieving an instruction of a device driver for the local device across the network. The remote node includes a local/remote bridge (e.g., an IB/PCI bridge). The host connects to the remote node and determines a configuration of the node's local communication bus and the local input/output device. A host memory address is mapped to a local bus address and is used by the input/output device to exchange data with the host.

Abstract: A method and apparatus are described by which interrupts from a source may be processed at a dynamically selectable level of priority. A system that has at least two different interrupt request connections, and that responds to interrupts asserted on the different connections by processing interrupts at associated and corresponding different priority levels, is configured so that an interrupt asserted by a particular interrupt source is coupled to a particular one of the plurality of request connections that has been selected under software control. Selective coupling of interrupt source to interrupt request connection may be effected by providing a set of control bits associated with each particular interrupt source, the set consisting, for example, of one interrupt mask bit for each of the different selectable priorities. Control may optionally be provided to preclude simultaneous coupling of an interrupt source to incompatible interrupt request connections.

Abstract: A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-directional buses that connect between the plurality of processors and shared memory, with the central unit including arbitration logic and a series of multiplexers to determine which CPUs are granted access to shared buses, scheduling logic that works with the arbitration logic and multiplexers to determine which CPUs are granted access to the shared buses, and port logic for combining the CPU transmissions and determining if such transmissions are valid.

Abstract: A bus for supporting plural signal line configurations and the method to switch it, used to operate in a bus between the control chips to maintain its operation flexibility. When the data transfer load in between the control chips is suitable for the bi-direction transfer, the signal line configuration of the bi-direction transfer is selected. When the direction of the bi-direction transfer switches frequently, the other signal line configuration is selected. That is, the bus signal lines are divided into two parts, each part is in charge of the data transfer in each uni-direction to avoid the turn around cycle that impacts the transfer performance.

Abstract: Techniques to prevent interruption of operations performed by an I/O device. One advantage may be that the I/O device does not need to re-establish its interrupted operation (and waste the associated time to re-establish its interrupted operation). Accordingly, bus utilization efficiency may be improved.

Abstract: A system and process are disclosed for automatically resuming data communication using an IEEE-1394 PHY when communication is suspended because input bias is momentarily lost. The PHY determines whether data communication is suspended due to the PHY being disconnected from a network by checking the status of a connected flag. If the connected flag is still set to TRUE, the PHY was not intentionally disconnected from the network and it automatically attempts to resume communication by setting a resume flag to TRUE. The invention finds application in any type of communication device using the IEEE-1394 high-speed serial bus standard including audio and video sources, which may readily be connected to a personal computer for data storage or editing. The system and process may be implemented using software code and included within a digital signal processor (DSP).

Abstract: A data processing module having a central processing unit and a task management control method and apparatus is disclosed which may comprise: a plurality of task identifiers adapted to identify a task requesting service by the central processing unit; an arbitration system external to the central processing unit adapted to select a task identifier from one of the plurality of task identifiers and to provide to the central processing unit the location of data or at least one instruction, which location is determined by the identity of the task identifier and to provide to the central processing unit the location of at least one instruction to initiate processing of the task, comprising: arbitration value determination logic adapted to determine at least one arbitration value of each task identifier requesting service; arbitration logic adapted to select a task identifier requesting service based upon the at least one arbitration value for each task identifier requesting service.

Abstract: Techniques are provided for simultaneously ascertaining the status of a plurality of devices coupled to a data bus. A master device transmits at least one status request message over the data bus to a plurality of slave devices. In response, the plurality of slave devices transmit to the master device a status indicator message including a plurality of status indicators indicating statuses of the plurality of slave devices. The master device receives the status indicator message and ascertains the status of at least some of the plurality of slave devices by examining the status indicators. The status request message and/or status indicator message may be a message defined according to a protocol associated with the data bus. The data bus may, for example, be a serial data bus such as an I2C bus.

Abstract: One embodiment of the present invention provides a system that facilitates atomically updating selected bits within a register in a computing system. During operation, the system receives a command to update selected bits within the register. This command includes a data word and a control bit pattern. Next, the system examines the control bit pattern to determine an operation to be performed on the register. The system then performs the operation, which involves using the dataword to modify a content of the register atomically, without blocking subsequent commands to update the register.

Abstract: An apparatus and method for generating distributed traffic in nodes coupled to a bus, wherein one node reads information on other nodes and generates traffic, includes a bus interface unit and a control unit receiving signals. The signals are transmitted from the nodes via the bus interface unit, to detect a bus reset and determine the number N of nodes coupled to the bus and a node ID number K of a node having the control unit. The information on the nodes is read in a predetermined order, starting from a reference node with node ID number K+M, wherein M is an integer larger than 1?K and smaller than N?K. The apparatus controls the order of generation of read transactions in each node for reading information from the other nodes coupled to a bus. The traffic load applied to each node is distributed to reduce an initial bus stabilization time.

Abstract: The present invention provides a method and apparatus for configuring an external device. The method comprises receiving configuration information, and providing at least a portion of the configuration information to the external device through a platform-independent interface. The apparatus comprises a storage unit adapted to store a platform-independent routine and a platform-independent interface, and a control unit adapted to execute the platform-independent routine, wherein the platform-independent routine causes the control unit to receive configuration information, and configure a Universal Serial Bus (USB) device through the platform-independent interface using at least the portion of the configuration information.

Abstract: A plug-and-play(PnP) interconnection architecture and method with an in-device storage module in a peripheral device are proposed for interconnecting a peripheral device with a host computer unit. The proposed architecture is characterized by integration of an in-device storage unit with internal functional modules of the peripheral device for storing device specific data and software such as the dedicated device driver of the peripheral device. An enhanced plug-and-play (ePnP) layered structure is proposed based on the in-device storage architecture. The ePnP provides a mechanism to PnP peripheral devices' functions customization. An application of the ePnP is the mechanism to bring up the device driver automatically when the peripheral device is connected to the host computer unit. This auto-installation mechanism provides a truly plug-and-play capability to the user.

Abstract: A method and system transfer read data from a memory device having a data bus and a data masking pin adapted to receive a masking signal during write operations of the memory device. The method includes placing a sequence of read data words on the data bus and applying a data bus inversion signal on the data masking pin, the data bus inversion signal indicating whether the data contained each read data word has been inverted. Another method and system transfer data over a data bus. The method includes generating a sequence of data words, at least one data word including data bus inversion data. The sequence of data words is applied on the data bus and is thereafter stored. The data bus inversion data is applied to invert or not invert the data contained in the stored data words.