Abstract: An apparatus and method are provided for operating a PCI-X bus. A device may be provided to determine a number of PCI-X cards coupled to the bus. A mechanism may be provided to control a frequency of the PCI-X bus based on the determined number of PCI-X cards coupled to the bus.
Abstract: In apparatuses (1, 2, 3) controlled or operated via an I2 C bus, it may be necessary to take measures to suppress interference signals at the data signal input/output of the respective apparatus without impairing the data transport at the same time. The data line at the data signal input/output contains an RC element, in the form of a low-pass filter, with a diode connected in parallel with the RC element, the low-pass filter action allowing the arrangement to be used to suppress interference signals acting on the data signal input/output, and, secondly, the transmissive action of the diode meaning that the arrangement does not impair a data signal leaving the data signal input/output.
Abstract: A method and apparatus for handling multiple processing streams in parallel on a single thread of a processing device. In one embodiment, a parallel processing agent includes a scheduler that multiplexes a number of processing streams, or pipelines, on a single thread of execution.
Abstract: Apparatus and method for providing a multiplexed bus supporting the coupling of either one of a device having a first bus type interface and a device having a second bus type interface where the multiplexed bus is made up, at least in part, of a plurality of common signal lines that may be coupled to either type of device, and that may be used to carry out transfers with protocols and timings for either bus.
Abstract: A method and an apparatus to combine and to send data dynamically are presented. The method comprises receiving data that partially satisfies a read request from a memory in response to a request, wherein the request is from a requester. The method further comprises forwarding the data to the requester if a port used to forward the data of the read request is idle. If the port is busy, the data is stored for combining with additional data that partially satisfies the read request as the additional data is received, and the combined data is forwarded to the requester when the port is not busy. In one embodiment, the port is a PCI Express™ port.
Type:
Grant
Filed:
March 31, 2003
Date of Patent:
February 14, 2006
Assignee:
Intel Corporation
Inventors:
Kenneth C. Creta, Sridhar Muthrasanalluar
Abstract: Peer-to-peer Direct Memory Access (DMA) permits the efficient transfer of data from one DMA capable Application Specific Integrated Circuit (ASIC) block to another without accessing memory. The peer-to-peer transfer can be done over a standard AMBA AHB bus architecture without side band signals and without violating the AHB specification.
Abstract: A method and apparatus are provided for efficiently managing hot spots in a resource managed computer system. The system utilizes a controller, a series of requestor groups, and a series of loan registers. The controller is configured to allocate and is configured to reallocate resources among the requestor groups to efficiently manage the computer system. The loan registers account for reallocated resources such that intended preallocation of use of shared resources is closely maintained. Hence, the computer system is able to operate efficiently while preventing any single requestor or group of requestors from monopolizing shared resources.
Type:
Grant
Filed:
December 17, 2003
Date of Patent:
February 7, 2006
Assignee:
International Business Machines Corporation
Abstract: Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.
Type:
Grant
Filed:
May 9, 2003
Date of Patent:
February 7, 2006
Assignee:
Hewlett-Packard Development Company, L.P.
Inventors:
Richard W. Adkisson, Christopher Alan Greer
Abstract: A point-to-point interconnection and communication architecture, protocol and related methods. System resources are dynamically shared based on contents of information received for transmission within the system. Virtual channels may be used for transmission of the information received for transmission over a general input/output (GIO) bus.
Abstract: The present invention relates to a management agent that can be ran on any operating system. More specifically, the management agent of the present invention is implemented with a set of application program interfaces (APIs) that allows the management agent to be independent of operating systems. The APIs makes the management agent portable across multiple operating systems. In an embodiment of the present invention, a Compact Peripheral Component Interconnect (CPCI) computer system includes a CPCI chassis, a circuit board located within the CPCI chassis, a first central processing unit (CPU) card coupled with the circuit board. The CPCI computer system also includes a second CPU card coupled with the circuit board, a first management agent located within the first CPU card, and a second management agent located within the second CPU card. The first and second CPU cards each respectively has a first operating system and a second operating system.
Type:
Grant
Filed:
August 26, 2003
Date of Patent:
January 31, 2006
Assignee:
Sun Microsystems, Inc.
Inventors:
Tuan A. Le, Christopher J. Rinaldo, Angshuman Mukherjee, Vinh N. Truong, Daniel Delfatti
Abstract: A flash-card exchanger has two modes of operation. When a host personal computer (PC) is connected to a Universal-Serial-Bus (USB) connector, the flash-card exchanger operates in a card reader mode, allowing the host to read data from removable flash-memory cards inserted into connector slots of the flash-card exchanger. When the host PC is not connected, a USB flash-memory thumb or key-chain drive can be inserted into a second USB connector. A USB dual-mode microcontroller acts as a USB host, reading data from the removable flash-memory card and writing the data to the USB-memory key drive using USB packets. Since the USB-memory key drive is small and removable, the user can upgrade to larger storage capacities by plugging in a larger-capacity USB-memory key drive. A flash-exchanger program executing on the USB dual-mode microcontroller copies data from an input-output bus and generates USB packets to the USB-memory key drive.
Type:
Grant
Filed:
January 15, 2004
Date of Patent:
January 31, 2006
Assignee:
Super Talent Electronics, Inc.
Inventors:
Ben Wei Chen, Tzu-Yih Chu, Sun-Teck See
Abstract: An arbitration unit includes an input unit, a selection unit and an output unit. The input unit may receive a plurality of input requests on a plurality of inputs. The selection unit may prioritize inputs into a priority order and may also select up to two of the input requests having a higher priority than others of the plurality of input requests during a current arbitration cycle. The output unit may provide an output indicative of which of the plurality of input requests were selected. During a subsequent arbitration cycle, the selection unit may reprioritize the plurality of inputs depending upon which of the plurality of input requests were selected.
Abstract: A method and device is described for transmitting information on a bus system having at least two users, as well as a bus system, exactly one superordinate user (master) and at least one subordinate user (slave) being provided, and the information being transmitted in a definable, closed message frame which, in addition to the information to be transmitted, also contains synchronization information, different information being uniquely assigned different information identifiers; after each closed message frame, a number of information sections being provided in which the at least one subordinate user may enter information.
Abstract: A small computer system interface (SCSI) system and methods of configuring/operating the SCSI system without cables. The SCSI system includes a system board, a backplane, and a cableless element configured to couple the system board to the backplane. The system board comprises an embedded SCSI controller configured to provide cableless control in each of a simplex mode of operation and a duplex mode of operation. The backplane comprises a plurality of connectors configured to couple SCSI devices to the backplane. The cableless element is configured to facilitate the exchange of control signals and power signals between the system board and the backplane in each of the simplex mode of operation and the duplex mode of operation, thereby providing a cableless embedded simplex/duplex SCSI system.
Type:
Grant
Filed:
July 29, 2003
Date of Patent:
January 17, 2006
Assignee:
Hewlett-Packard Development Company, L.P.
Abstract: A disk array controller is made up of multiple disk array control units for implementing the data read/write operation and each having channel IF units, disk IF units, cache memory units and shared memory units. The disk array controller further includes inter connections for interconnecting the shared memory units and interconnecting the cache memory units across the border of disk array control units. Thereby alleviating the deterioration of performance due to the data transfer between the disk array control units, when the multiple disk array control units are to be operated as a single disk array controller.
Abstract: The present invention creates dedicated point-to-point or point-to-multipoint links between different devices along plural busses. Synchronized clocks to each device enable proper timing of read and write operations to/from the bus. The bus connection between the devices are selectively switchable so that dedicated bus connections between devices can be switched on and off as needed. Since the links are point-to-point between sending and receiving devices, the throughput of star-like topology (e.g., Ethernet) can be achieved with very low latency. An arbiter creates the link. The link is established indefinitely, for as long as the arbiter configures it to exist. Additional transactions through the link require only a frame signal to be asserted by the sender and the frame signal to be interpreted as a“data ready” signal by the target.
Abstract: A data bus bridge circuit and method are provided for coupling a slave device with a data bus in a system in which data words are transferred between a master device and the slave device over the data bus. The bridge circuit removes master-induced stalls of burst transfers by converting those burst transfers into a plurality of separate, independent sub-bursts.
Abstract: A method and apparatus for moderating packet ingress interrupts. A network interface includes a packet timer and an absolute timer or absolute counter. The packet timer functions to minimize packet latency during periods of low packet ingress at the network interface. Each of the absolute timer and absolute counter functions to minimize CPU load and packet latency during periods of high packet ingress at the network interface.
Abstract: The utility of portable computer hosts, such as PDAs (or handhelds), is enhanced by methods and apparatus for removable expansion modules (100) having application specific circuitry, a second-level-removable memory (120), and optional I/O (140), in a number of illustrative embodiments. In addition to providing greater expansion utility in a compact and low profile industrial design, the present invention permits memory configuration versatility for application specific expansion modules, permitting easy user field selection and upgrades of the memory used in conjunction with the expansion module. Finally, from a system perspective, the present invention enables increased parallelism and functionality previously not available to portable computer devices.
Abstract: A method for reducing interrupt latency in a data processing system wherein a storage device is provided having a predetermined maximum number of storage locations. Data execution circuitry is coupled to the storage device for providing data to the storage device and storing the data in the storage device. Interrupt control circuitry is coupled to the data execution circuitry, wherein the interrupt control circuitry interrupts the data execution circuitry. The data stored in the storage device is completely outputted, thereby having an associated interrupt latency resulting from the output of the stored data. The storage capacity of the storage device is changed dynamically to minimize the interrupt latency. The storage device has a utilization value that varies between a predetermined minimum number of storage locations and the predetermined maximum number of storage locations based upon an operating mode of the data processing system.