Patents Examined by Gopal C. Ray
  • Patent number: 7043590
    Abstract: A PCI interface card coupled to a PCI bus includes a first controller and a second controller. When a processor coupled to the PCI bus initializes the PCI interface card, the first controller is enabled to respond with a message to the processor to indicate that the PCI interface card is a single-function device and the second controller is disabled. When the processor disables the first controller, the second controller is allowed to connect the processor through the first controller. A computer system includes the processor, the PCI bus, and the PCI interface card.
    Type: Grant
    Filed: May 28, 2004
    Date of Patent: May 9, 2006
    Assignee: Realtek Semiconductor Corp.
    Inventors: Shien-Ming Huang, Shang-Yii Huang, Hsin-I Chou
  • Patent number: 7043583
    Abstract: A method of processing a frame of a CPU intensive communications protocol includes disabling per frame interrupts of a CPU; enabling a periodic interrupt handler to interrupt the CPU upon an interrupt period; and upon an interrupt of the periodic interrupt handler, determining and processing a frame received in the interrupt period. Further, a frame sent acknowledgment stored in the interrupt period may be processed during the interrupt. A method of processing the transmission of frames of a CPU intensive communications protocol includes, when no MSU frame is queued for transmission, sending FISU frames that each point to itself; and if a MSU frame is queued for transmission, updating the MSU frame to point to a new FISU frame, updating a current FISU frame to point to the MSU frame, and sending the current FISU frame, the MSU frame and the new FISU frame.
    Type: Grant
    Filed: October 28, 2004
    Date of Patent: May 9, 2006
    Assignee: Intel Corporation
    Inventor: Dhananjay A. Nagalkar
  • Patent number: 7039745
    Abstract: A control system having improved maintainability and operability is provided. To this end, in a control system comprising a plurality of field devices distributed in equipment and a controlling input/output device, and a host controller connected to the plurality of field devices via a transmission line and controlling the field devices, the field devices and the host controller constituting a network in the equipment for control of the equipment, the control system further comprises a plurality of connectors for connecting the plurality of field devices to the transmission line, the connectors having network IDs representing respective connected positions to the network, and a node address creating unit for generating node addresses based on the network IDs.
    Type: Grant
    Filed: April 26, 2004
    Date of Patent: May 2, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Yuuichi Hagino
  • Patent number: 7035952
    Abstract: A system includes plural storage subsystems each having a controller and an expander to couple to storage devices. The controller accesses the storage devices through the expander, and the expander has interfaces for coupling to the storage devices. The system further includes an intercontroller link to connect expanders in two storage subsystems to enable the controller in one of the storage subsystems to communicate with the controller in another one of the storage subsystems through the expanders and the intercontroller link.
    Type: Grant
    Filed: September 24, 2003
    Date of Patent: April 25, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert C. Elliott, Thomas Grieff, Joseph E. Foster
  • Patent number: 7035951
    Abstract: A system and method for auto-addressing devices on a multiplexing bus in which a plurality of devices are arranged in series, with each having a bus in and bus out. During an initial evaluation, and beginning with a low bus in, each device inverts the incoming signal so that a device with a low bus in has a high bus out. During a second evaluation, the high or low state of the bus in is inverted only if the bus out in the first evaluation was high. Similarly, during subsequent evaluations, the high or low state of the bus in is inverted only if the bus out state of all previous evaluations was high. Ultimately, only one device will have a high bus out, with all bus out states from previous evaluations also having been high, at which point all addresses are fully decoded.
    Type: Grant
    Filed: December 4, 2003
    Date of Patent: April 25, 2006
    Assignee: Saia-Burgess Automotive Inc.
    Inventors: Tanh M. Bui, Reiner E. Stockfisch, Tobias Taufer
  • Patent number: 7035957
    Abstract: A PCI bridge circuit connects to first and second PCI buses and performs data transfer between PCI devices. The PCI bridge circuit has a data buffer and controller and the controller 70, prior to the establishment of a data transfer state with the first PCI device via the first PCI bus, receives data from the second PCI device via the second PCI bus into a data buffer and inserts a wait state. Consequently while reducing the capacity of the data buffer, data transfer between PCI devices can be performed without affecting the transfer performance.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: April 25, 2006
    Assignee: Fujitsu Limited
    Inventor: Yasuo Ishiwata
  • Patent number: 7032056
    Abstract: Methods and apparatus are disclosed for use in an electronic system where data is transmitted over signaling conductors from one electronic component to another using strobe signals accompanying the data. The edge or transition of the strobe signals identifies when, in a window of time, the receiving electronic component should latch the data. In many such systems, data is transmitted over the signaling conductors in the form of a plurality “beats”, of data, proper timing to latch each beat of data being identified by a transition of the strobe signal. Faults in components or errors in transmission must be handled. The present invention discloses apparatus and methods to communicate conditions relevant to data transmitted without requiring additional signaling conductors. The present invention discloses selecting a message from a plurality of messages, encoding the selected message, and transmitting the encoded message on existing strobe lines to communicate the condition encountered.
    Type: Grant
    Filed: May 8, 2003
    Date of Patent: April 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: William Hugh Cochran, William Paul Hovis
  • Patent number: 7032053
    Abstract: A method and system for providing a running image of an operating system on a removable operating system module to multiple computer systems. The removable operating system module includes a memory unit for storing the running image of the operating system. Upon insertion of the module into a computer system, a BIOS loads the operating system from the removable operating system module and initiates the execution of the operating system. In response to a request by the user, the BIOS may resume or restart the operating system. The operating system may also discover any available local and remote devices, resume any available previously running applications, and perform tasks requested by the applications and the user. In response to a user's removal request, the state of the operating system is saved on the module and the removable operating system module is removed from the computer system.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: April 18, 2006
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Andrew Himmel, Maria Azua Himmel, Herman Rodriguez
  • Patent number: 7032063
    Abstract: A multi-port Fibre Channel controller according to embodiments of the present invention includes a number of Fibre Channel ports, an interface unit coupled to each one of the Fibre Channel ports, a Fibre Channel controller, and a processor. The processor is coupled to the Fibre Channel controller, and the Fibre Channel controller is coupled to control the interface unit and coupled to the subsystem interface.
    Type: Grant
    Filed: July 30, 2004
    Date of Patent: April 18, 2006
    Assignee: Vicom Systems, Inc.
    Inventor: Dietmar M. Kurpanek
  • Patent number: 7028133
    Abstract: Method and apparatus are described for improving information transfer over USB. In one approach, hub-based extension is realized wherein power is distributed using auxiliary wiring distinct from signal and power wiring present in conventional USB cabling. Additional signals allow optimization of power distribution for powering attached devices, and for detecting and handling illegal connection configurations. In another approach, improvements are realized through use of alternative signaling techniques which eschew reflective and high-speed common-mode signaling. Described are various configuration, media and signal-protocol combinations, including implementations containing embedded hubs. Methods ensuring reliable system behavior are also described, including determination of extension path delay and use of topology-enforcement hubs.
    Type: Grant
    Filed: April 28, 2000
    Date of Patent: April 11, 2006
    Inventor: Daniel Kelvin Jackson
  • Patent number: 7028130
    Abstract: A system having a PCI Express fabric and PCI devices connected thereto transmits data from the PCI devices having PCI Express traffic classes assigned. A PCI Express to PCI bridge assigns a predetermined address to the grant line for each PCI device coupled to the PCI bus and stores this address along with the data from the PCI device in the PCI transaction queues. When the data is transmitted along the PCI Express fabric, or when it is processed within the PCI Express to PCI bridge, the address assigned to the respective grant line becomes the PCI Express traffic class for that data. This enables the commands from one device to be processed irrespective of commands from other PCI devices on the PCI bus.
    Type: Grant
    Filed: August 14, 2003
    Date of Patent: April 11, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Andrew W. Lueck, Kevin K. Main
  • Patent number: 7024508
    Abstract: Described is a bus station (e.g., a sensor, an actuator, a gateway) which performs a primary device function and a secondary function (e.g., a bus monitor function). To perform the secondary function, the bus station is equipped with a bus monitor arrangement which allows the bus station to access, to detect and to further process telegram traffic carried on the bus system. Also described is a network equipped with a plurality of such bus stations and a method for carrying out such monitoring with the aid of the bus stations.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: April 4, 2006
    Assignee: Vega Grieshaber KG
    Inventors: Thomas Gros, Fridolin Faist
  • Patent number: 7020725
    Abstract: A method for reserving an isochronous resource over a link between a first bus and a second bus, the link including a first interface device connected to the first bus and a second interface device connected to the second bus. The reservation of the resources over the link is transparent to the devices connected to the busses. The method includes, at the level of the interface devices, intercepting the connection set up messages sent by the devices connected to the busses, checking whether a source device and a sink device for which the set-up message has been intercepted are on different busses, and in the affirmative, reserving resources for the connection over the link.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: March 28, 2006
    Assignee: Thomson Licensing
    Inventors: Nicolas Burdin, Sébastien Perrot, Christophe Vincent
  • Patent number: 7016992
    Abstract: The present invention provides a system capable of individually controlling each of receiving devices while making full use of the advantages of broadcasting. Simultaneous transmission is carried out from a broadcasting device 2 to a plurality of receiving devices 6 via a broadcasting path. Further, the broadcasting device 2 sends operation control data to the receiving device 6 through a communication path. The receiving device 6 changes its operation in accordance with the operation control data when received broadcasting is decoded. In this way, each of the receiver devices 6 can be controlled individually using the operation control data while making full use of the advantages of broadcasting.
    Type: Grant
    Filed: August 15, 2001
    Date of Patent: March 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Keisei Yamamuro, Tatsuya Shimoji, Yuki Kusumi, Yasushi Nishimura, Kazuo Okamura, Yasunori Tanaka
  • Patent number: 7010639
    Abstract: An inter-integrated circuit port comprising an electrical connector for communicatively coupling to an I2C bus and a controller coupled to the electrical connector. The controller controls data communication flow through the electrical connector, including preventing the electrical connector from unauthorized access to the data.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: March 7, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thane M. Larson, Kirk Bresniker
  • Patent number: 7010641
    Abstract: A method of routing an integrated circuit signal bus is provided. One of a set of blocks having ports that are to be connected to the signal bus is selected as a primary block, the ports of which are positioned so that no two ports of that block lie within the same routing track parallel to the closest portion of a primary bus route. All other blocks, termed secondary blocks, have ports that are positioned so that no two ports of any secondary block reside within the same routing track perpendicular to the closest portion of the primary bus route. A primary connection for each signal of the signal bus is then placed over each port of the primary block substantially along the length of the primary route. Each port of each secondary block then has a secondary track connecting it in a perpendicular fashion to the proper primary track.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: March 7, 2006
    Assignee: Agilent Technologies, Inc.
    Inventors: Gerald L Esch, Jr., Richard S. Rodgers
  • Patent number: 7010631
    Abstract: A controller based hardware device includes a controller node for each of a plurality of hardware elements, and a control instruction decoder. The control instruction decoder is arranged for receiving control data for a specific one of the hardware elements and communicating that control data to the associated hardware element. The control data includes at least one control vector, which includes at least one command line and an indication of the scheduling of the command lines. The command line includes at least one operation which may be executed in parallel on the controller based hardware. The operation includes a description of data flow between selected one of the hardware elements.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: March 7, 2006
    Assignee: Eonic B.V.
    Inventor: Nicholas C. Kopp
  • Patent number: 7010638
    Abstract: A bridge controller controls the data flow to/from a USB bus to/from an ATA/ATAPI drive, such as an ATA hard drive or ATAPI CD or DVD drive. The bridge controller has a state machine which receives the CBW in a background mode in real time as the packet is being transferred to the bridge controller. The state machine uses the CBW to set up the data transfer. The bridge controller also has a programmable processor which is coupled to the CBW once it is received in a buffer memory. The programmable processor makes changes in the set up of the receiving device for the transfer, if needed, and initiates the data transfer.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: March 7, 2006
    Assignee: Texas Intruments Incorporated
    Inventors: Brian Tse Deng, Dinghui Richard Nie, Joseph M. Erickson
  • Patent number: 7007126
    Abstract: An I/O subsystem having a processor, a bridge unit, and an I/O messaging unit that couple a primary, secondary and tertiary bus in a computer system. The bridge unit is configurable to claim requests that access a messaging unit (MU) address range from the secondary bus, the MU itself being coupled to the primary bus. The MU interrupts the processor when an I/O request is posted, in response to which the processor reads from the MU pointers to an I/O messages and may then execute the I/O message. To promote the portability of software written for agents on either the primary or the secondary bus that wish to access the MU, the primary and secondary address translation units of the I/O subsystem are programmed to claim the same address translation window, where the MU address range is a portion of the primary ATU address translation window, and the secondary ATU is configured to not claim requests within the MU address range.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventors: Byron R. Gillespie, Barry R. Davis, William Futral
  • Patent number: 7003611
    Abstract: A method, apparatus, and computer instructions for managing interrupts using a set of presentation controllers. A first interrupt server is identified in the set of interrupt servers to handle the interrupt in response to receiving an interrupt signal. The set of interrupt servers constituting a server pool are linked in a circular list using a set of identifiers. The message representing the interrupt is sent to a second interrupt server, such as in a second presentation controller in the set of presentation controllers based on an identifier identifying the second interrupt server in the set of interrupt servers, if the first interrupt server is unable to handle the interrupt. The identifier is found within the first interrupt controller. The interrupt is passed to different interrupt servers potentially associated with different presentation controllers within the circular list.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventor: Richard Louis Arndt