Abstract: An integrated circuit has a multi-layer stack such as a gate stack or a digit line stack disposed on a layer comprising silicon. A conductive film is formed on the transition metal boride layer. A process for fabricating such devices can include forming the conductive film using a vapor deposition process with a reaction gas comprising fluorine. In the case of a gate stack, the transition metal boride layer can help reduce or eliminate the diffusion of fluorine atoms from the conductive film into a gate dielectric layer. Similarly, in the case of digit line stacks as well as gate stacks, the transition metal boride layer can reduce the diffusion of silicon from the polysilicon layer into the conductive film to help maintain a low resistance for the conductive film.

Abstract: A method for generating an optical proximity correction (OPC) model includes generating a set of correction rules for a wafer design containing at least one of lines and assist features, determining a set of corrections that need to be made over a range of sizes and spaces of the lines and assist features based on the set of correction rules, and creating an optical proximity correction model for correcting the wafer design based on the set of corrections.

Abstract: A method of forming an electrically conductive plug in an opening in a dielectric layer of a substrate. Silane is thermally decomposed so as to deposit a layer of material on the walls of an opening. Subsequently, electrically conductive material is deposited so as to fill the opening.

Abstract: An improved pre-clean chamber of a semiconductor processing system minimizes the generation of particulates during processing, thereby decreasing contamination levels that can adversely affect plasma vapor deposition film properties while also decreasing operational costs. The pre-clean chamber comprises an insulator collar that insulates the outside diameter surface of a wafer pedestal, thereby mitigating the etching of the wafer pedestal during etching. The pre-clean chamber further comprises a gas trench cover that directs a suitable etching gas from a gas inlet trench into streams that are focused up and towards the center of the chamber to reduce the extent to which gas bombards the chamber cover. The pre-clean chamber also comprises a bellows cover which protects the bellows of a wafer lift during etching, further reducing the dislodgment of particulates during etching.

Abstract: A cross point memory array is fabricated on a substrate with a plurality of memory cells, each memory cell including a diode and an anti-fuse in series. First and second conducting materials are disposed in separate strips on the substrate to form a plurality of first and second orthogonal electrodes with cross points. A plurality of semiconductor layers are disposed between the first and second electrodes to form a plurality of diodes between the cross points of the first and second electrodes. A passivation layer is disposed between the first electrodes and the diodes to form a plurality of anti-fuses adjacent to the diodes at the cross points of first and second electrodes. Portions of the diode layers are removed between the electrode cross points to form the plurality of memory cells with rows of trenches between adjacent memory cells to provide a barrier against crosstalk between adjacent memory cells. The trenches extend substantially to the depth of the n-doped layer in each diode.

Abstract: A system, method and computer program features of the present invention, relate to verification or simulation of a design using a behavioral model structure for use in a Client/Server configuration. A physical part presents the external interface, and a functional procedural part which is comprised of at least one VHDL process. A testcase is a set of procedure calls written in VHDL. The present invention describes the architecture and implementation of a client/server behavioral model and procedural approach for testcase development which results in significant gain in productivity, quality of logic verification, and portability.

Abstract: A square poly-spacer and making of the same are disclosed. The square poly-spacer is formed adjacent a floating poly-gate sharing a common source line with another floating poly-gate. The common source line comprises polysilicon and is separated from the floating poly-gate by an intervening oxide spacer. The square poly-spacer is also separated from the floating gate by an intergate oxide layer, and serves as a control gate and communicates with a salicided word line formed over the square top of the poly-spacer. It is shown that a square poly-spacer can be formed advantageously by first chemical mechanical polishing a poly spacer and then performing an etch back of the polysilicon, rather than just performing an etch back only. The square top, rather than the continuously contoured sloping wall, prevents the bridging that can occur over a curved poly spacer to the substrate when a portion of the poly spacer surface is salicided to obtain a well behaving word line.

Abstract: A method of forming an oxide layer on a substrate comprises deposition of a mask layer with an opening for defining the area where the oxide layer is to be formed, and an ion implantation step performed with a tilt angle so as to obtain a varying ion concentration. In a subsequent single oxidation step, an oxide layer is formed having a thickness that varies in conformity with the ion concentration. This method may advantageously be applied to the formation of a gate insulation layer in a field effect transistor.

Abstract: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;<˜3.0). Preferably, the cavities are provided with an elemental titanium-free liner to facilitate cavity filling, and the cavities are filled with CVD aluminum that is introduced into the cavities by way of a forcefill at pressures ranging from atmospheric to about 50 MPa, and preferably no more than about 30 MPa, at temperatures ranging from about 100°-300° C. Cavities filled in the foregoing manner exhibit electrical resistance levels that are up to 30% less than structures filled by conventional practices.

Abstract: Embodiments of the present invention include a method of depositing an improved seasoning film. In one embodiment the method includes, prior to performing a substrate processing operation, forming a layer of silicon over an interior surface of the substrate processing chamber as opposed to a layer of silicon oxide. In certain embodiments, the layer of silicon comprises at least 70% atomic silicon, is deposited from a high density silane (SinH2n+2) process gas and/or is deposited from a plasma having a density of at least 1×1011 ions/cm3.

Abstract: A system and method for calibrating/characterizing an electron beam (e-beam) defect inspection tool for detecting voltage contrast defects includes deliberately forming defects in a test portion of a semiconductor wafer by deliberately forming an open, short, or abnormal resistance in a circuit feature. The test portion can be in the scribe lines of a product die or on a fully populated test wafer, so that the calibration of the e-beam tool for certain inspection layers of a fabrication technology can be determined. The electron microscope output of the is checked against the known defects to determine whether the tool is accurately sensing defects.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: For a semiconductor device including a gate electrode in an area of part of a surface of a semiconductor substrate, a gate length is determined and to be set as an upper-limit gate length. For a semiconductor device of which a gate length is almost equal to the upper-limit gate length, an impurity implantation condition is determined to calculate a representative impurity concentration distribution. A limit gate length is obtained according to the representative impurity concentration distribution. For a semiconductor device of which a gate length is equal to or greater than the limit gate length and equal to or less than the upper-limit gate length, an impurity concentration distribution of the semiconductor device is calculated according to the representative impurity concentration distribution. Characteristics of the semiconductor device are obtained according to the impurity concentration distribution. This method reduces the period of time to calculate the characteristics of the semiconductor device.

Abstract: A method for producing a laminate having resin layers and thin metal layers by repeating a process unit comprising a step of laminating a resin layer by applying a resin material, a step of depositing a patterning material on the resin layer and a step of laminating a thin metal layer, predetermined times on a turning support (511), wherein the patterning material is stuck on the surface of the resin layer in a noncontact way. A laminate comprising a large number of laminate units each comprising a resin layer and a thin metal layer divided at an electric insulation stripe part can be produced stably. The laminate is applicable to production of a high performance small capacitor at low cost.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.

Abstract: A CMOS structure and method of achieving self-aligned raised source/drain for CMOS structures on SOI without relying on selective epitaxial growth of silicon. In the method, CMOS structures are provided by performing sacrificial oxidation so that oxidation occurs on the surface of both the SOI and BOX interface. This allows for oxide spacer formation for gate-to-source/drain isolation which makes possible raised source/drain fabrication without increasing contact resistance.

Abstract: The present invention discloses a polycrystalline silicon thin film transistor connected to a gate line and a data line that includes a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer positioned between and contacting the source and the drain electrodes, and acting as a channel area in which electrons flow; at least one metal layer positioned near the polysilicon layer and parallel to a flow direction of the electrons; and a buffer layer interposed between the metal layer and the polysilicon layer.

Abstract: For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.

Abstract: High quality dielectric layers, e.g., high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are formed by electrolessly plating a metal or metal-based dielectric precursor layer comprising at least one refractory or lanthanum series transition metal, such as of Zr and/or Hf, on a silicon-based semiconductor substrate and then reacting the precursor layer with oxygen or with oxygen and the Si-based semiconductor substrate to form the at least one metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.