Abstract: A method for forming self-aligned split gates in a flesh memory is disclosed. The method includes two-step lithographic definition of a split gate and nitride spacer formation of the gate. The two-step lithography procedure is designed to assist the nitride spacer formation. The nitride spacer formation is used to facilitate gate etching in a self-aligned manner so that the channel length of the split gate is under proper control and the effect of gate misalignment can be totally avoided. The product quality of the flesh memory therefore gets improved.

Abstract: The present invention provides a method for manufacturing a plurality of buried metal lines on a semiconductor substrate. The method comprises the steps as below. A dielectric layer is formed on a semiconductor substrate. And a plurality of insulator blocks are formed on the dielectric layer, wherein each the insulator block has a width of 3 unit (3×), and each gap between two adjacent the insulator blocks has a width of 5 unit (5×). First sidewall spacers are formed on sidewalls of the insulator blocks, wherein each the first sidewall spacer has a width of 1 unit (1×). Then the plurality of the insulator blocks are removed, and second sidewall spacers are defined on sidewalls of the first sidewall spacers, wherein each the second sidewall spacer has a width of 1 unit (1×). Next studs are formed into gaps between two adjacent the second sidewall spacers, wherein each the stud has a width of 1 unit (1×). And the second sidewall spacers are removed.

Abstract: A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

Abstract: A method of inspecting a semiconductive wafer-in-process to determine the accuracy of alignment of a lower process layer to an upper process layer. In this method, a conductive target attribute is formed on a first alignment portion of the wafer-in-process. A contact attribute is formed on the upper process layer through which an electric path can be established with the target attribute in an acceptable alignment situation but cannot established in an unacceptable alignment situation. By attempting to establish an electric path from the target attribute through the contact attribute, the accuracy of alignment can be determined based on whether or not an electrical path is established. The target attribute may be a series of conductive strips and the contact attribute may be a series of contact holes that will overlay the corresponding target attributes in differing degrees in an acceptable alignment situation.

Abstract: A method for fabricating an integrated circuit which reduces steps in the integrated circuit comprising the steps of depositing a first conductive material layer over the first dielectric material layer and patterning the first conductive material layer to form a first conductive pattern. A second dielectric layer is then deposited over the first conductive pattern and the exposed portions of the first dielectric material layer. A planarizing material layer is applied over the second dielectric material layer and cured such that the planarizing material layer produces a substantially planar top surface. The planarizing material layer and portions of the second dielectric material layer are removed in a manner which maintains the substantially planar top surface until only a preselected amount of material remains over the first conductive pattern.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: A semiconductor device comprises a substrate having a first thermal expansion coefficient T1, a strain reducing layer formed on the substrate and having a second thermal expansion coefficient T2, and a semiconductor layer formed on the strain reducing layer, having a third thermal expansion coefficient T3, and made of a nitride compound represented by AlyGa1−y−zInzN (0≦y≦1, 0≦z ≦1). The second thermal expansion coefficient T2 is lower than the first thermal expansion coefficient T1. The third thermal expansion coefficient T3 is lower than the first thermal expansion coefficient T1 and higher than the second thermal expansion coefficient T2.

Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Abstract: Annealing technology is capable of heating a wafer on which a copper film is formed at a desired temperature within a short period of time. A light-shielding plate 106 of SiC (silicon carbide) exhibiting a flat emissivity irrespective of the wavelengths and emitting light over a wide band of wavelengths is interposed between the wafer 1 on which is formed a copper film having a high light reflection factor and lamps 102. The lamps 102 are turned on in this state so that the light-shielding plate 106 is heated, first, and, then, the wafer 1 is heated by light radiated from the light-shielding plate 106 that is heated, thereby to anneal the copper film.

Abstract: A semiconductor wafer has a front side 1, a back side 2, a top layer 3, a bottom layer 4, an upper inner layer 5 lying beneath the top layer 3, an lower inner layer 6 lying above the bottom layer 4, a central region 7 between the layers 5 and 6, and an uneven distribution of crystal lattice defects. The crystal lattice defects are substitutionally or interstitially included nitrogen or vacancies.

Abstract: An aperture body has a light transmissive region defined therein which includes first, second, third and fourth curved segments. During an exposure process, each curved segment of the light transmissive region contributes to an improved resolution and optimum depth of focus (DOF).

Abstract: A method of fabricating a CMOS transistor to construct shallow drain extenders (30) using a replacement gate design. The method involves forming epitaxial layers (30) and (220) the will later function as shallow drain extensions. The etching of the replacement gate (220) and the formation of inner sidewalls (90) serve to define the transistor gate length.

Abstract: A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.

Abstract: The present invention relates to a semiconductor laser device and a method for fabrication thereof, wherein the semiconductor laser device exhibits an improved mode selectivity.

Abstract: An image sensor having a plurality of pixels arranged in a series of row and columns comprising: a semiconductor substrate having a plurality of pixels formed in rows and columns with at least two row adjacent pixels and at least two column adjacent pixels formed within the substrate; and at least one electrical function integrated within the adjacent pixels that is shared between the adjacent pixels. The electrical function can be either a contact region or an electrical circuit used in implementing either a photogate, a transfer gate, a reset gate, a row select gate, an amplifier drain, an output node, a floating diffusion contact, a reset drain, a lateral overflow gate, an overflow drain or an amplifier.

Abstract: A built-in circuit for wafer level burn-in of a die. The burn-in circuit includes a main burn-in control circuit, a word line control circuit and a bit line control circuit. A number of internal probing pads are also provided to receive voltages for stressing a gate oxide or capacitor oxide layer. A burn-in test system has a plurality of programmable power suppliers and programmable relays for providing control and power signals to a membrane or micro spring probe card used for the wafer level burn-in of multiple dice at the same time. Wafers are loaded and aligned in a prober with an automatic probing station and a hot chuck for the burn-in. The wafer level burn-in reduces the burn-in time of an integrated circuit chip from several days to several minutes.

Abstract: A method for forming a crystal layer including the steps of (1) supplying first impurity atoms onto a surface of a crystal substrate to form a surfactant layer adsorbed on the surface, (2) supplying nucleus atoms which bond with the first impurity atoms, (3) repeating step (2) until second impurity atoms are supplied in step (4), and (4) supplying second impurity atoms which bond with the first impurity atoms and the nucleus atoms to epitaxially grow a crystal layer including the nucleus atoms as a crystal nucleus material doped with the first and second impurity atoms. A co-dopant having a three-atom composite formed by supplying the atoms on the surface of the crystal enables smooth doping thereof to produce the crystal having the high density dopant or a low resistance.

Abstract: A semiconductor device is manufactured by a method including the steps of forming a through hole in an interlayer dielectric layer (silicon oxide layer, BPSG layer, etc.) formed on a semiconductor substrate having a device element. A barrier layer is formed on surfaces of the interlayer dielectric layer and the through hole. A wiring layer is formed on the barrier layer. The barrier layer is formed by a method including the following steps. A titanium layer that forms at least a part of the barrier layer is formed. A heat treatment is conducted in a nitrogen atmosphere to form a titanium nitride layer at least on a surface of the titanium layer. The titanium nitride layer is contacted with oxygen in an atmosphere including oxygen. A heat treatment is conducted in a nitrogen atmosphere to form titanium oxide layers and to densify the titanium nitride layer.

Abstract: The solid-state image sensor comprises a semiconductor substrate, a plurality of photoelectric conversion sections formed within respective isolated active regions on the semiconductor substrate, an image area wherein unit cells comprising the plurality of photoelectric conversion sections and a signal scanning circuit are arranged in a two-dimensional array form, and signal lines for reading signals from the respective unit cells within the image pick-up area, wherein the respective photoelectric conversion sections being formed by at least two ion implantations.

Abstract: A wafer level packaging method which produces a stacked dual/multiple die integrated circuit package. In the method, the wafer with the smaller sized dice of two wafers is processed through a metal redistribution process and then solder balls are attached. The wafer is then sawed into individual die size ball-grid array packages. On the wafer with the larger sized dice, a die attached adhesive material is deposited on the front of each die site location that is intended for the attachment of one of the die-sized BGA packages. The back side of the BGA die package is placed onto the adhesive material and is cured. A wirebonding operation connects the signals from the die-size BGA package to the circuits of the bottom die. A coating material, such as epoxy, is disposed on the wafer to cover the wirebond leads and the assembly is then cured. Then, the stacked-die wafer is singulated into individual stacked-die IC packages.