Abstract: A method for electrically coupling thermoelectric cooling (TEC) elements together is described. The TEC elements are encased within an encapsulating material, such as epoxy, and a resist layer is laid on either end of the encapsulating material, covering the ends of the TEC elements. The resist layers are selectively developed to open locations in the resist layers in between adjacent elements. Conductive material, such as gold, is sputter deposited into the locations to provide electrical coupling of the elements.

Abstract: There are provided a semiconductor laser, a semiconductor light emitting device, and methods of manufacturing the same wherein a threshold current density in a short wavelength semiconductor laser using a nitride compound semiconductor can be reduced. An active layer is composed of a single gain layer having a thickness of more than 3 nm, and optical guiding layers are provided between the active layer and cladding layers respectively.

Abstract: A method of fabricating a diode device, such as a PIN diode, includes forming top and bottom regions of opposite conductivity types and includes anisotropically etching into the top surface to form a pit having side walls that converge with approach to the bottom surface. However, the pit does not extend to the bottom surface. In the PIN diode embodiment, the pit terminates within an intrinsic region that separates a bottom surface diffusion region from a diffusion region along the walls of the anisotropically etched pit. The anisotropic etching approach provides a degree of self regulation with regard to the geometries of the pit. A process flow of steps is described, which allows thicker and larger diameter wafers to be used in the formation of an array of such diode device.

Abstract: A field-effect transistor has a composite channel structure having a first channel layer containing GaInP semiconductor and a second channel layer containing GaAs semiconductor. When the electric field is low in the channel, a channel current is primarily conducted in the second channel layer. When the electric field is high, the electrons flowing in the second channel layer move through real space transition to the first channel layer. These electrons conduct in the channel primarily in the first channel layer. Since GaInP semiconductor has a wider forbidden bandwidth than that of GaAs semiconductor, the avalanche breakdown voltage of GaInP semiconductor is higher than that of GaAs semiconductor. When the electric field is high, the conduction electrons travel in this GaInP semiconductor layer. This also improves the avalanche breakdown voltage of the field-effect transistor.

Abstract: The data flows of a system are allocated an arithmetic or logical function per function block (ALU-block), forming a RAM control. The ALU-blocks are specialized according to individual processing tasks of the data flows. The current status of the Ram address and RAM output data are recoupled with the ALU-blocks. During operation, the ALU-blocks alternately produce write accesses to the RAM and read accesses of all the ALU blocks can occur with every cycle, thereby controlling the outgoing signal lines of the data flows. Registers are inserted in such a way that the ALU-blocks are placed between register levels to ensure that test patterns are generated automatically with existing CAE programs. The low use of test structures guarantees that the base circuit has good testability with a minimal test pattern rate at an early stage of the circuit design. The inventive circuit structure can also be configured as a digital signal processor.

Abstract: An extraction grid for field emitter tip structures and method of forming are described. A conductive layer is deposited over an insulative layer formed over the field emitter tip structures. The conductive layer is milled using ion milling. Owing to topographical differences along an exposed surface of the conductive layer, ions strike the exposed surface at various angles of incidence. As etch rate from ion milling is dependent at least in part upon angle of incidence, a selectivity based on varying topography of the exposed surface (“topographic selectivity”) results in non-uniform removal of material thereof. In particular, portions of the conductive layer in near proximity to the field emitter tip structures are removed faster than portions of the conductive layer between emitter tip structures. Thus, portions of the insulative layer in near proximity to the field emitter tip structures may be exposed while leaving intervening portions of the conductive layer for forming the extraction grid.

Abstract: A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

Abstract: A semiconductor device includes a bonding layer which consists of an intermetallic compound and is positioned between a first electrode and a bump electrode. The bump electrode is mainly made of Au. The intermetallic compound of the bonding layer consist of Au of the bump electrode and a low melting metal.

Abstract: A method of forming a contact in an integrated circuit is disclosed herein. The method includes providing a first insulating layer over a semiconductor substrate including first and second gate structures, providing an etch stop layer over the first insulating layer, providing a second insulating layer over the etch stop layer, creating a first aperture in the second insulating layer between the first and second gate structures, creating a second aperture in the first insulating layer below the first aperture, and filling the first and second apertures with a conductive material to form the contact. The first aperture has a first aperture width and extends to the etch stop layer. The second aperture has a second aperture width which is less than the first aperture width.

Abstract: A system for processing a workpiece includes a head attached to a head lifter. A workpiece is supported in the head between an upper rotor and a lower rotor. A base has a bowl for containing a liquid. The head is movable by the head lifter from a first position vertically above the bowl, to a second position where the workpiece is at least partially positioned in the bowl. The bowl has a contour section with a sidewall having a radius of curvature which increases adjacent to a drain outlet in the bowl, to help rapid draining of liquid from the bowl. The head has a load position, where the rotors are spaced apart by a first amount, and a process position, where the rotors are engaged and sealed against each other. For rapid evacuation of fluid, the head also has a fast drain position, where the rotors are moved apart sufficiently to create an annular drain gap.

Abstract: Provided is a method of integrating Ta2O5 into an MIS stack capacitor for a semiconductor device by forming a thin SiON layer at the Si/TaO interface using low temperature remote plasma oxidation anneal. Also provided is a method of forming an MIS stack capacitor with improved electrical performance by treating SiO2 with remote plasma nitridation or SiN layer with rapid thermal oxidation or RPO to form a SiON layer prior to Ta2O5 deposition with TAT-DMAE, TAETO or any other Ta-containing precursor.

Abstract: A method of creating a resist or other protective material pattern on a substrate using traversal of a focused energy beam such as a laser beam in a selected pattern over the substrate to cure a resin polymer, other resist material or other protective layer disposed over the substrate. The substrate may comprise a semiconductor wafer or other large-scale substrate comprising a large plurality of semiconductor die locations, may comprise a partial wafer or substrate, or a singulated semiconductor die.

Abstract: This invention relates to the field of semiconductor integrated circuits and, particularly to stand-alone and embedded memory chips fabricated on Silicon-on-Insulator (SOI) substrates and devices. Partially depleted (PD) and fully depleted (FD) devices are utilized on the same chip. The invention is a process flow utilizing fully depleted SOI devices in one area of the chip and partially depleted SOI devices in selected other areas of the chip. The choice of fully depleted or partially depleted is solely determined by the circuit application in that specific area of the chip. The invention is able to be utilized in accordance with DRAM processing, and especially embedded DRAMs with their large proportion of associated logic circuitry.

Abstract: A gate-controlled device includes an inverted-T gate which overlaps lightly doped, shallow extension regions formed in an underlying base layer. Spacers are included on the sides of the gate, and source/drain regions are formed in the base layer in non-overlapping relationship with the gate layer. This device outperforms conventional devices in terms of performance. Lower external resistance is achieved by forming a gate-controlled inversion channel over at least a portion of the shallow LDD extensions, and by making the shallow LDD extensions graded (or sloped) towards the deep source/drain regions. Also, forming portions of the gate underneath the spacers, electrical gate control of the shallow LDD junctions is made possible. This advantageously reduces the series resistance of the device and increases drive current, both of which translate into improved device performance with no increase in gate-to-source/drain parasitic capacitance.

Abstract: A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.

Abstract: A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysterisis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system.

Abstract: The invention provides a method for fabricating bitlines, including the following steps: providing a semiconductor substrate having a contact opening, which opening exposed a diffusion region in the substrate or a polysilicon layer of a wordline; forming a polysilicon layer to cover the opening and contacting the exposed surface of the diffusion region or the polysilicon layer of the wordline; forming a tungsten silicide layer to cover the polysilicon layer; performing a ion implantation step with high energy and high dosage to damage a contact surface between the bitline and the wordline or a contact surface between the bitline and the diffusion region; forming a better contact surface between the bitline and the wordline or a better contact surface between the bitline and the diffusion region using thermal annealing in the subsequent steps, thereby reducing contact resistance between the bitline and the wordline or between the bitline and the diffusion region.

Abstract: A dam for substantially laterally confining a quantity of encapsulant material over a region of a substrate, such as an interposer. The dam is configured to protrude upwardly from a surface of the interposer or other substrate. The interposer may be positioned at least partially around a slot or aperture through the substrate so as to laterally confine encapsulant material over the slot or aperture and over any intermediate conductive elements extending through the slot or aperture. The dam may be fabricated by stereolithography. A package including the interposer, the dam, and a semiconductor die to which the interposer is secured may include a sealing element between the interposer and the active surface of the die. All or part of the sealing element may also be fabricated using stereolithography. Methods and systems using machine vision in conjunction with stereolithography equipment are also disclosed.

Abstract: A substrate such as a sapphire substrate or the like is set to a molecular beam epitaxy (MBE) apparatus. Next, the temperature of the substrate is elevated to the temperature which is lower than the temperature at which a predetermined ZnO based oxide semiconductor layer (i.e. function layer) is grown (S1). Then, raw materials containing oxygen radical is irradiated to the substrate to grow a buffer layer made of ZnO based oxide semiconductor (S2). Subsequently, the irradiation of oxygen radical is stopped so as to eliminate the influence of oxygen onto the buffer layer (S3). Then, the temperature of the substrate is elevated to the temperature at which the predetermined ZnO based oxide semiconductor layer is grown (S4). After that, raw materials containing oxygen radical is irradiated so as to sequentially grow a ZnO based oxide semiconductor layer as a function layer (S5).

Abstract: An apparatus and method for depositing a thin film on a semiconductor substrate. The apparatus includes a chamber or housing suited for holding a plurality of wafer platforms. The wafer platforms are arranged stacked in the chamber equidistant and electrically isolated from each other wafer platform. At least two of the plurality of wafer platforms are electrically coupled to a power source to form a first electrode and a second electrode. The remainder of the plurality of wafer platforms are disposed therebetween. In this manner, the first electrode and the second electrode form a single series capacitor. At least one reactant gas is provided in the chamber and reacted with sufficiently supplied energy to form a plasma. Radicals or ions from the plasma react on the surface of the wafers to cause a thin film layer to be distributed on the equally dispersed wafers positioned on a surface of the wafer platforms.