Abstract: Process for producing electrical-connections on a semiconductor package containing an integrated-circuit chip and with an external protective layer having apertures that least partly expose metal electrical-connection regions, and semiconductor package provided with such metal electrical-connections. The apertures having walls are filled with a metal electrical-connection layer covering at least their walls. A metal solder drop is soldered to the connection layer so that it is not in contact with the external protective layer.

Abstract: Bridging between nickel silicide layers on a gate electrode and source/drain regions along silicon nitride sidewall spacers is prevented, after silicidation and removal of any unreacted nickel, by treating the exposed surfaces of the silicon nitride sidewall spacers with a HDP plasma to oxidize nickel silicide thereon forming a surface layer comprising silicoin oxide and silicon oxynitride. Embodiments include treating the silicon nitride sidewall spacers with a HDP plasma to form a surface silicon oxide/silicon oxynitride region having a thickness of about 40 Å to about 50 Å.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: A system for processing a workpiece includes a base having a bowl or recess for holding a liquid. A sonic energy source, such as a megasonic transducer, provides sonic energy into a liquid in the bowl. A process reactor or head holds a workpiece between an upper rotor and a lower rotor. A head lifter lowers the head holding the workpiece into the liquid. Sonic energy is provided to the workpiece through the liquid, optionally while the head spins the workpiece. The liquid may include de-ionized water and an etchant.

Abstract: A system and method for providing substantially defect free rapid thermal processing. The present invention includes a wafer processing system used to process semiconductor wafers into electronic devices. In accordance with the present invention, once the wafer is processed, a shield can be inserted into the reactor to a position between the reactor heating surface and the wafer. The shield causes the temperature of the wafer to be reduced. Once the temperature of the wafer has been reduced to below a predetermined critical temperature, the robot picks up the wafer and removes the wafer from the processing chamber.

Abstract: In a computer-implemented synthesis system, a method of optimizing a design of an integrated circuit device. The optimization process includes the computer-implemented steps of accessing a circuit netlist representing an integrated circuit design to be realized in physical form, wherein the circuit netlist includes a top-level block and at least a first and a second circuit block. The top-level block includes glue logic for coupling the first and second circuit blocks. The process creates a first model of the first circuit block and a second model of the second circuit block, the first model and the second model each operable for independently abstracting embodying circuitry of the first and second circuit blocks, respectively. The circuit netlist is optimized by independently optimizing the first circuit block and the second circuit block, and the top-level block to yield a fully optimized circuit netlist. The first and second circuit blocks are both independently optimized.

Abstract: A system for processing a workpiece includes a base having a bowl or recess for holding a liquid. A process reactor or head holds a workpiece between an upper rotor and a lower rotor. A head lifter lowers the head holding the workpiece into contact with the liquid. Sonic energy is introduced into the liquid and acts on the workpiece to improve processing. The head spins the workpiece during or after contact with the liquid. The upper and lower rotors have side openings for loading and unloading a workpiece into the head. The rotors are axially moveable to align the side openings.

Abstract: A method of converting ball grid array (BGA) modules to column grid array (CGA) modules comprises steps of heating a BGA module, brushing the BGA module to remove the balls, and attaching columns to the module to create a CGA module. A method of converting a first CGA module to a second CGA module comprises steps of heating the first CGA module, brushing the first CGA module to remove the columns, and attaching columns to the module to create the second CGA module.

Abstract: This invention discloses the present invention discloses a junction field effect transistor (JFET) device supported on a substrate. The JFET device includes a gate surrounded by a depletion region. As the distance between the gates is large enough, there is a gap between the depletion regions surrounding adjacent gates. Depletion mode JFET transistor which is normally on is provided. The normally on transistors respond to negative bias applied to the gates to shut of the current path in the substrate. The current path in the substrate is normally available with a zero gate bias. As the distance between the gates is reduced, the JFET transistor is normally off because the depletion regions surround the gates shut of the current channel. The depletion region responding to a positive bias applied to the gate to open a current path in the substrate wherein the current path in the substrate is shut off when the gate is zero biased.

Abstract: A method to form asymmetric MOS transistors using a replacement gate design. The method involves forming implanted regions (140) and (145) in the channel region after removal of the replacement gate structure (110) to produce high threshold voltage regions and low threshold voltage regions.

Abstract: A reticle has a main pattern to be transferred to a photo-sensitive layer and surrounded by a non-transparent layer, and a discriminative pattern loops in the non-transparent layer so as to define an area to be inspected for serious defects, wherein the discriminative pattern is implemented by plural non-transparent portions such as strips arranged at intervals less than the minimum width to be transferred at the maximum resolution of the reduction projection aligner; however, the discriminative pattern or the plural non-transparent portions occupy a looped area wider than a minimum width to be recognized by a pattern recognition system so that the discriminative pattern clearly defines the area to be inspected regardless of the resolution.

Abstract: An apparatus and method used in extracting polysilicon gate doping from C−V analysis in strong inversion, especially for ultrathin gate oxides. For sub-20-angstrom oxide MOS devices, transistors with channel lengths less than about 10 &mgr;m are connected in parallel to avoid an extrinsic capacitance roll-off in strong inversion. The upper limit of the channel length is estimated using a transmission-line-model of the terminal capacitance, which accounts for the non-negligible gate tunneling current and finite channel resistance.

Abstract: One of the greatest challenges in C/C++-based design methodology is to efficiently map C/C++ models into hardware. Many of the networking and multimedia applications implemented in hardware or mixed hardware/software systems are making use of complex data structures stored in one or multiple memories. As a result, many of the C/C++ features which were originally designed for software applications are now making their way into hardware. Such features include dynamic memory allocation/deallocation and pointers used to manage data. This inventors present a solution for efficiently mapping arbitrary C code with pointers and malloc/free into hardware. This solution fits current memory management methodologies. It consists of instantiating a hardware allocator tailored to an application and a memory architecture. This work also supports the resolution of pointers without restriction on the data structures.

Abstract: A method for designing an ASIC has a first step of generating circuit data that includes a large-scale hardware macro made up of primitive macros; a second step of extracting, from the circuit data generated in the first step, wiring data of an external terminal of the large-scale hardware macro, an output of which is in an open state or an input of which is clamped; a third step of performing circuit tracing using the wiring data of the external terminal extracted in the second step; a fourth step of removing wiring data of a redundant primitive macro and redundant wiring data connected to said redundant primitive macros using the wiring data of the external terminal extracted in the second step; a fifth step of generating a temporary library in which a delay time within the macro is adjusted, based on removal results obtained in the fourth step; and a sixth step of performing layout and wiring, and of performing a delay simulation, using the temporary library generated in the fifth step.

Abstract: Conductive structures and methods for preparing conductive structures are provided. Conductive structures according to the present invention can be prepared by controllably deforming and shaping a metal layer by using a hydrogen gas source and thermally treating the hydrogen gas source.

Abstract: A first option is a method of forming an ultra thin buffer oxide layer comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided. The silicon substrate has an upper surface. A sacrificial oxide layer is formed over the silicon substrate and the STI regions. Oxygen is implanted within the silicon substrate. The oxygen implant having a peak concentration proximate the upper surface of the silicon substrate. The sacrificial oxide layer is stripped and removed. A gate dielectric layer is formed over the silicon substrate. A conductor layer is deposited over the gate dielectric layer. The structure is annealed to form ultra-thin buffer oxide layer between the silicon substrate and the gate dielectric layer. A second option is a method of forming an ultra-thin buffer oxide layer, comprises the following steps. A silicon substrate having STI regions formed therein separating at least one active area is provided.

Abstract: Information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit are inputted through circuit information I/O portion. Enable logic timing constraint generating portion generates timing constraint to be secured for enable logic. Enable logic timing determination portion calculates a delay time in the enable logic and determines whether or not the enable logic satisfies the timing constraint based on the delay time. Clock gating execution portion, when the enable logic satisfies the timing constraint, adds a gating circuit and a circuit composed of the enable logic to a logic circuit not clock-gated so as to generate a clock-gated logic circuit. Circuit information I/O portion outputs information about the clock-gated logic circuit and timing constraint to be secured for the enable logic.

Abstract: A semiconductor integrated circuit having an input protection device which is suitable for receiving inputs of signals having voltages higher than the internal power supply voltage is provided. The input protection device consists of an offset NMOS transistor in which one of heavily doped N-type diffusion layers is electrically connected to a signal input terminal of the semiconductor integrated circuit. In the NMOS transistor, the field isolation structure is a trench structure, and the heavily doped N-type diffusion layers are offset from the gate electrode. Since a parasitic bipolar action easily occurs according to this construction, the protective function against overcurrent caused by static electricity or the like is not impaired. Since signal voltages are by no means applied directly to the gate oxide of the protection device during normal operation, signals with voltages higher than the internal power supply voltage can be input.

Abstract: A lead frame including signal-connecting leads, a die pad and support leads is provided. A semiconductor chip is bonded to the die pad with an adhesive. The semiconductor chip, electrode pads and the signal-connecting leads are electrically connected to each other with metal fine wires. And these members are encapsulated in a resin encapsulant. The back surface of the die pad is subjected to half etching or the like to form a convex portion and a flange portion surrounding the convex portion. Since a thin layer of the resin encapsulant exists under the flange portion, the resin encapsulant can hold the die pad more strongly and the moisture resistance of the device can be improved with the lower surface of the die pad protruding from the resin encapsulant. As a result, the characteristics of a resin-molded semiconductor device having a die pad exposed on the back surface of a resin encapsulant can be improved.

Abstract: An optical device and a method for manufacturing the optical device. An optical device having a molded-package structure includes: a lead frame having a ferrule-mounting portion; a ferrule mounted on the ferrule-mounting portion; and a molding resin that encapsulates the lead frame and the ferrule, molding, except that an end of the ferrule protrudes through and outside of the surface of the molding resin. The first groove parallel to a longitudinal axis of the ferrule is located on the ferrule-mounting portion and the ferrule is placed on the first groove. Thus, the ferrule is hardly ever detached from a ferrule-mounting portion, an optical fiber is hardly ever damaged, and an optical coupling is hardly ever obstructed.