Abstract: A hierarchal storage management method is provided. The method includes detecting a first portion of a first file being deleted from a hybrid storage device including a hard disk drive (HDD) memory device, a solid state drive (SSD) memory device, and an archival storage memory device. A first set of memory blocks associated with the first portion of the first file is identified. The first set of memory blocks are determined to reside on the SSD memory device. In response, the first set of memory blocks are transferred from the SSD memory device to a first portion of the hybrid storage device.

Abstract: The flow cache of a network flow processor (NFP) stores flow lookup information in cache lines. Some cache lines are stored in external bulk memory and others are cached in cache memory on the NFP. A cache line includes several lock/hash entry slots. Each slot can store a CAM entry hash value, associated exclusive lock status, and associated shared lock status. The head of a linked list of keys associated with the first slot is implicitly pointed to. For the other lock/entry slots, the cache line stores a head pointer that explicitly points to the head. Due to this architecture, multiple threads can simultaneously process packets of the same flow, obtain lookup information, and update statistics in a fast and memory-efficient manner. Flow entries can be added and deleted while the flow cache is handling packets without the recording of erroneous statistics and timestamp information.

Abstract: The present disclosure includes apparatuses, methods, and systems for data relocation in hybrid memory. A number of embodiments include a memory, wherein the memory includes a first type of memory and a second type of memory, and a controller configured to identify a subset of data stored in the first type of memory to relocate to the second type of memory based, at least in part, on a frequency at which an address corresponding to the subset of data stored in the first type of memory has been accessed during program operations performed on the memory.

Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted to the processor unit instead of the requested data as a response to the read request, and the processor unit replaces the pattern tag with the corresponding data pattern.

Abstract: A storage device includes a nonvolatile storage and a controller. The controller is configured to compress data received from a host in association with a write command designating a first data length as a length of the data and a starting logical address of the data, into compressed data of a second data length shorter than the first data length, write the compressed data in the nonvolatile storage. Further, the controller is configured to generate an address mapping for the data, such that a first logical address range that starts at the starting logical address is mapped to a physical region of the nonvolatile storage having a size equal to the second data length, and a second logical address range that directly follows the first logical address range is not mapped to any physical region of the nonvolatile storage.

Abstract: System and method for managing storage replication consistency groups for storage objects of processing entities uses a replication group identifier for a storage replication consistency group received from a storage interface manager of a storage system with multiple computer data storage devices. The replication group identifier is received when a creation request for a new logical storage unit for a processing entity is transmitted from a host computer to the storage interface manager. The replication group identifier can then be used to request additional logical storage units that will be assigned to the same storage replication consistency group.

Abstract: A method for providing redundancy in a virtualized storage system for a computer system is provided. The method includes determining a first set of first logical addresses to provide a virtual storage volume. A redundancy schema is then selected to provide redundancy data for primary data stored in the first set of first logical addresses. A second set of second logical addresses is determined to provide logical storage for the primary data and for the redundancy data. The first set of first logical addresses and the second set of second logical addresses are then mapped and a set of physical addresses is selected from a set of physical storage elements. Mapping between the second set of second logical addresses and the set of physical addresses is then performed to provide physical storage for the primary data and the redundancy data stored in the virtual storage volume.

Abstract: Hardware memory management units are used in an integrated safety/non-safety industrial computer to allow shared memory architecture processors to implement safety and non-safety reduced risk of memory corruption. Testing of the memory management unit of the non-safety processor may provide a periodic writing to protected memory to invoke a protection fault providing a report to the safety processor.

Abstract: Remote copy operations are performed to copy data from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress, and wherein consistency groups are formed during the remote copy operations to copy the data consistently. Quiescing of I/O operations performed via the bus interface are performed while a current consistency group is being replaced by a next consistency group during the remote copy operations.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: Apparatuses and methods of manufacturing same, systems, and methods for a spatial memory streaming (SMS) prefetch engine are described. In one aspect, the SMS prefetch engine includes a pattern history table (PHT), which has a table in which each entry has an offset list field comprising sub-fields for offset values from a base offset value within a region and a per-offset confidence field comprising sub-fields for per-offset confidence levels corresponding to each offset value. When a PHT entry is activated, the per-offset confidence values corresponding to each offset value in the offset list field of the PHT entry are updated by matching current accesses to the stored offset values in the offset list field of the activated PHT entry. Continuous learning may be provided to the SMS engine at least by the per-offset confidence levels.

Abstract: System and methods for detecting events based on data object attributes in a storage system are described.

Abstract: A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

Abstract: A method of controlling an ultra-deep power down (UDPD) mode in a memory device, can include: receiving a write command from a host via an interface; beginning a write operation on the memory device to execute the write command; reading an auto-UDPD (AUDPD) configuration bit from a status register; switching the interface to a Single SPI mode in response to the write command and the AUDPD configuration bit being set; completing the write operation on the memory device; automatically entering the UDPD mode upon completion of the write operation in response to the AUDPD configuration bit being set; and entering a standby mode upon completion of the write operation in response to the AUDPD configuration bit being cleared.

Abstract: Implementations of this disclosure are directed to systems, methods and media for assessing the status of data being stored in distributed, cached databases that includes retrieving, from a data cache, variables which include a cache loss indicator and a non-null value. The variables are analyzed to determine a state of the cache loss indicator. If the cache loss indicator indicates an intentional cache loss state, the cache loss indicator is removed and the non-null value is provided to an application. Otherwise, a cache restore process is initiated.

Abstract: A storage system includes a storage unit having a plurality of routing circuits electrically networked with each other, each of the routing circuits being locally connected to a plurality of node modules, each of which includes nonvolatile memory, the plurality of node modules forming at least first and second storage regions, and a plurality of connection units, each connected to one or more of the routing circuits, and access the first and second storage regions through one or more of the routing circuits in accordance with a command. When one of the connection units receives a command to write second data into the first storage region while first data are being read out from the first storage region, said one of the connection units writes the second data into both the first and second storage regions.

Abstract: A memory system may include a first memory having a first operating speed, and a second memory having a second operating speed which is different from the first operating speed. A compression device may compress data of the first memory, and may transfer the compressed data to the second memory. The compression device may select a compression scheme among a plurality of compression schemes based on at least one characteristic of the data of the first memory and a data processing combination selected among a plurality of data processing combinations between a series of data processing units of the first memory and a series of data processing units of the second memory, and may compress the data of the first memory according to the selected compression scheme.

Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

Abstract: A memory module operable to communicate data with a memory controller via a data bus comprises a plurality of memory integrated circuits including first memory integrated circuits and second memory integrated circuits, a data buffer coupled between the first memory integrated circuits and the data bus, and between the second memory integrated circuits and the data bus, and logic coupled to the data buffer. The logic is configured to respond to a first memory command by providing first control signals to the data buffer to enable communication of at least one first data signal between the first memory integrated circuits and the memory controller through the data buffer, and is further configured to respond to a second memory command by providing second control signals to the data buffer to enable communication of at least one second data signal between the second memory integrated circuit and the memory controller through the data buffer.

Abstract: An illustrative pseudo-file-system driver uses deduplication functionality and resources in a storage management system to provide an application and/or a virtual machine with access to a locally-stored file system. From the perspective of the application/virtual machine, the file system appears to be of virtually unlimited capacity. The pseudo-file-system driver instantiates the file system in primary storage, e.g., configured on a local disk. The application/virtual machine requires no configured settings or limits for the file system's storage capacity, and may thus treat the file system as “infinite.” The pseudo-file-system driver intercepts write requests and may use the deduplication infrastructure in the storage management system to offload excess data from local primary storage to deduplicated secondary storage, based on a deduplication database.