Abstract: A method, apparatus and product for utilizing address translation structures for testing address translation cache. The method comprises: obtaining a first address translation structure that comprises multiple levels, including a first top level which connects a sub-structure of the first address translation structure using pointers thereto; determining, based on the first address translation structure, a second address translation structure, wherein the second address translation structure comprises a second top level that is determined based on the first top level, wherein the second top level connects the sub-structure of the first address translation structure; executing a test so as to verify operation of an address translation cache of a target processor at least by: adding a plurality of cache lines to the address translation cache, wherein said adding is based on the address translation structures; and verifying the operation of the address translation cache using one or more memory access operations.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: Provided are a computer program product, system, and method for providing track access reasons for track accesses resulting in the release of prefetched cache resources for the track. A first request for a track is received from a process for which prefetched cache resources to a cache are held for a second request for the track that is expected. A track access reason is provided for the first request specifying a reason for the first request. The prefetched cache resources are released before the second request to the track is received. Indication is made in an unexpected released track list of the track and the track access reason for the first request.

Abstract: Techniques for accessing off-heap memory are disclosed. The system may receive a memory segment layout definition for a memory segment in a physical memory of a machine. The memory segment layout definition defines a number of elements and a number of sub-elements in each element of the plurality of elements. The system may allocate the particular memory segment in the physical memory and may store a reference to a position of a sub-element. The system may receive a request to access a first sub-element of a particular element of the plurality of elements. Based on the request, the system may identify the memory segment corresponding to the plurality of elements, identify the particular element of the plurality of elements, identify the first sub-element of the plurality of elements based the position of the first sub-element, and execute an Input or Output (IO) operation corresponding to the request.

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

Abstract: A cache coherent system includes a directory with more than one snoop filter, each of which stores information in a different set of snoop filter entries. Each snoop filter is associated with a subset of all caching agents within the system. Each snoop filter uses an algorithm chosen for best performance on the caching agents associated with the snoop filter. The number of snoop filter entries in each snoop filter is primarily chosen based on the caching capacity of just the caching agents associated with the snoop filter. The type of information stored in each snoop filter entry of each snoop filter is chosen to meet the desired filtering function of the specific snoop filter.

Abstract: A tag check performed for a memory access operation comprises determining whether an address tag associated with a target address of the access corresponds to a guard tag stored in the memory system associated with a memory system location to be accessed. A given tag check architecturally required for a tag-checked load operation can be skipped when a number of tag-check-skip conditions are satisfied, including at least: that there is an older tag-checked store operation awaiting a pending tag check, for which a guard tag checked in the pending tag check is associated with a same block of one or more memory system locations as a guard tag to be checked in the given tag check; and that the address tag for the tag-checked load operation is the same as the address tag for the older tag-checked store operation.

Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.

Abstract: A storage device includes a nonvolatile memory device including a first region and a second region, and a controller that receives a first operation command including move attribute information and a first logical block address from an external host device and moves first data corresponding from the first region to the second region in response to the received first operation command, and when the first operation command does not include the move attribute information, the controller performs a first operation corresponding to the first operation command.

Abstract: Described herein are embodiments related to a two-stage hybrid memory buffer for multiple streams in memory sub-systems. A processing device determines that first write data of a first stream stored in a host buffer component satisfies a threshold to program a first programming unit. The processing device transfers the first write data to the staging buffer component from the host buffer component, and writes the first write data from the staging buffer component as the first programming unit to a first die of multiple non-volatile memory (NVM) dies. The processing device determines that second write data of a second stream satisfies a threshold to program a second programming unit, transfers the second write data to the staging buffer component from the host buffer component, and writes the second write data from the staging buffer component as the second programming unit to a second die of the multiple NVM dies.

Abstract: A method is described. The method includes receiving a read or write request for a cache line. The method includes directing the request to a set of logical super lines based on the cache line's system memory address. The method includes associating the request with a cache line of the set of logical super lines. The method includes, if the request is a write request: compressing the cache line to form a compressed cache line, breaking the cache line down into smaller data units and storing the smaller data units into a memory side cache. The method includes, if the request is a read request: reading smaller data units of the compressed cache line from the memory side cache and decompressing the cache line.

Abstract: A memory device includes a page cache comprising a cache register, a memory array configured with a plurality of memory planes, and control logic, operatively coupled with the memory array. The control logic receives, from a requestor, a first cache read command requesting first data from the memory array spread across the plurality of memory planes, and returns, to the requestor, data associated with a first subset of the plurality of memory planes and pertaining to a previous read command, while concurrently copying data associated with a second subset of the plurality of memory planes and pertaining to the previous read command into the cache register.

Abstract: Provided are a computer program product, system, and method for determining space to release in a target volume to which tracks from a source volume are mirrored. A copy of a source volume table for the source volume providing a state of the tracks in the source volume for a consistency group is received. Tracks received from the source volume are written to the target volume to form the consistency group of tracks in the source volume at the target volume. A determination is made of tracks available to release from the copy of the source volume table and space allocated to the determined tracks is replaced. A point-in-time copy is created of the target volume for the consistency group. Complete is returned to forming the consistency group in response to releasing the space and creating the point-in-time copy.

Abstract: An apparatus comprises memory storage circuitry comprising a plurality of memory storage locations to store data; an interface to receive an address from a requester; decryption circuitry to obtain a decrypted address by decrypting, based on a decryption key, an address received from the requester; and access control circuitry to select, based on the decrypted address obtained by the decryption circuitry, a memory storage location of the memory storage circuitry to be accessed.

Abstract: Provided are a computer program product, system, and method for determining tracks to release in a target volume mirroring tracks from a source volume. Tracks received from the source volume are written to the target volume to form a consistency group of tracks in the source volume at the target volume. A determination is made of tracks available to release from a volume table providing a state of the tracks in the target volume and space allocated to the determined tracks is released. A point-in-time copy of the target volume is crated and complete is returned to forming the consistency group in response to releasing the space and creating the point-in-time copy.

Abstract: A memory module includes a memory device, a command/address buffering device, and a processing data buffer. The memory device includes a memory cell array, a first set of input/output terminals, each terminal configured to receive first command/address bits, and a second set of input/output terminals, each terminal configured to receive both data bits and second command/address bits. The command/address buffering device is configured to output the first command/address bits to the first set of input/output terminals. The processing data buffer is configured to output the data bits and second command/address bits to the second set of input/output terminals. The memory device is configured such that the first command/address bits, second command/address bits, and data bits are all used to access the memory cell array.

Abstract: According to one aspect of the present disclosure a method and technique for managing data transfer includes receiving and storing a plurality of different data patterns anticipated to be encountered by a processor unit of a data processing system corresponding to a particular application being processed. Responsive to receiving a read request for data, the requested data is read from a memory subsystem, and the read data is compared by the memory subsystem to the stored data patterns. Responsive to determining that the read data matches at least one of the stored data patterns, the memory subsystem replaces the matching read data with a pattern tag corresponding to the matching data pattern. The pattern tag is transmitted over a communication link in response to the request.

Abstract: An information handling system may include a processor and a program of instructions embodied in non-transitory computer-readable media and configured to, when read and executed by the processor: in response to a request to write a variable to a solid state device, store the variable to a memory location of the solid state device, the variable including variable data and a variable status indicative of a validity of the variable data, the variable status having a plurality of bits wherein each of the plurality of bits are set to an initial value and in response to a request to modify the variable, modify the variable status by changing one of the plurality of bits from the initial value to a logical complement of the initial value to change the validity of the variable data. The validity of the variable data may be based on whether an even number or odd number of the plurality of bits are equal to the complement of the initial value.

Abstract: Embodiments herein provide for dynamic storage system configuration. In one embodiment, a storage controller is operable to configure a storage volume from a plurality of storage devices. The storage controller includes an interface operable to receive a first write I/O request from a host system, and to extract a storage configuration attribute from the first write I/O request. The storage controller also includes a processor communicatively coupled to the interface and operable to identify a storage configuration required by the first write I/O request based on the storage configuration attribute, to determine whether the storage volume comprises the required storage configuration of the first write I/O request, and to configure a portion of the storage volume according to the storage configuration required by the first write I/O request in response to a determination that the storage volume does not comprise the required storage configuration.

Abstract: A memory system includes a memory device, a write buffer for buffering first and second host data, a chip-kill cache for caching one among first and second chip-kill parity candidates for the first and second host data, respectively, a chip-kill buffer having a smaller bandwidth and a larger capacity than the chip-kill cache; a chip-kill manager for generating a first chip-kill parity by performing an XOR operation on the first host data and the first chip-kill parity candidate, and generating a second chip-kill parity by performing an XOR operation on the second host data and the second chip-kill parity candidate, and a processor for controlling the memory device to program the first host data and the first chip-kill parity into a first open block and to program the second host data and the second chip-kill parity into a second open block.