Abstract: A memory device includes a nonvolatile memory unit, a write buffer, and a controller. The controller is configured to receive a write command from a host, send a permission signal to the host after the write command is received, receive write data associated with a write command from the host in response to the permission signal, store the write data in the write buffer, and transfer the write data stored in the write buffer to the nonvolatile memory unit. The controller controls a timing of transmitting the permission signal, such that the write buffer is full for no longer than a predetermined length of time.

Abstract: A non-volatile memory (NVM) integrated circuit device includes an NVM array of memory cells partitioned into a first physical region to store a first firmware stack and a second physical region to store a second firmware stack. The NVM integrated circuit device also includes a processing device that enables a host microcontroller to execute in place the first firmware stack stored within a first set of logical addresses that is mapped to the first physical region. The processing device tracks accesses, by the host microcontroller, to the first set of logical addresses. The processing device, in response to detecting one of a certain number or a certain type of the accesses by the host microcontroller, initiates a recovery operation including to remap the first set of logical addresses to the second physical region.

Abstract: In one general embodiment, a computer-implemented method includes receiving, by the computer, a request to access a first magnetic recording tape. A determination is made, by the computer, whether the first magnetic recording tape is currently loaded in a tape drive. In response to determining that the first magnetic recording tape is not currently loaded in a tape drive, a determination is made, by the computer, of an amount of time to unmount and unload a magnetic recording tape from each of at least two tape drives each having a magnetic recording tape loaded therein. The tape drive with the shortest amount of time to unmount and unload the magnetic recording tape loaded therein is selected and instructed to unload the magnetic recording tape loaded therein. The first magnetic recording tape is caused to be loaded into the selected tape drive.

Abstract: A system and associated methodology for controlling block duplicates when deduplicating data (Dedup Blocks) to a storage space. The system includes a persistent database of known duplicates stored in the storage space (KD Table), and a non-persistent database of possible duplicates stored in the storage space (PD Table). Computer logic executes programming instructions stored in memory that are configured to index the KD Table according to a value derived from bits of a Dedup Block's hash signature, to index the PD Table according to another value derived by other bits of the Dedup Block's hash signature, to demote known duplicates from the KD Table to the PD Table, and to promote possible duplicates from the PD Table to the KD Table.

Abstract: A method, computer program product, and computer system for reducing, by a computing device, overlap in a RAID extent group by moving a first disk extent in an extent pool from a source disk to a target disk in a Mapped RAID group. A neighborhood matrix for the Mapped RAID group may be balanced by moving a second disk extent in the extent pool from the source disk to the target disk in the Mapped RAID group.

Abstract: A data storage device includes a memory controller and a memory device. The memory controller includes multiple memory blocks each including a first predetermined number of pages. In an SPOR procedure, the memory controller is configured to divide a destination memory block previously utilized in a garbage collection procedure that has not been finished into multiple sub-blocks each including a second predetermined number of pages, sequentially perform a binary search on one or more sub-blocks to determine a first empty page of the destination memory block, sequentially read one or more pages from the first empty page to determine a last valid page of the destination memory block, and re-perform the garbage collection procedure according to the last valid page. The second predetermined number is smaller than the first predetermined number and is a power of 2.

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; and offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; and detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element acces

Abstract: When a logical capacity of a nonvolatile semiconductor memory is increased, after a logical capacity which is allocated to a RAID group but unused is released, the RAID group is reconfigured to include the released logical capacity and the increased logical capacity. When the logical capacity of the nonvolatile semiconductor memory is reduced, after the reduced logical capacity is released from the RAID group, the RAID group is reconfigured with the released logical capacity.

Abstract: Management of storage used by pageable guests of a computing environment is facilitated. A query instruction is provided that details information regarding the storage location indicated in the query. It specifies whether the storage location, if protected, is protected by host-level protection or guest-level protection.

Abstract: Data processing circuitry comprises a cache memory to cache a subset of data elements from a main memory; a processing element to execute program code to access data elements having respective memory addresses, the processing element being configured to access the data elements in the cache memory and, in the case of a cache miss, to fetch the data elements from the main memory; prefetch circuitry, responsive to an access to a current data element, to initiate prefetching into the cache memory of a data element at a memory address defined by a current offset value relative to the address of the current data element; offset value selection circuitry comprising: an address table to store memory addresses for which a data element accessed by the processing element resulted in a cache miss or an access to a previously prefetched data element; detector circuitry to detect, for each of a group of candidate offset values, one or more respective metrics representing a proportion of a set of data element accesses whic

Abstract: A vehicular device includes: a function processing unit that executes an application software; a volatile memory that temporarily stores a backup data; and a backup processing unit that copies the backup data from the volatile memory to a non-volatile memory when an event for terminating an operation occurs. The function processing unit and the backup processing unit execute processes independently, and are accessible to a same memory space in the volatile memory, respectively. The function processing unit reads out the backup data from the volatile memory and reboots the application software when an event for maintaining an activation occurs while the backup processing unit is storing the backup data from the volatile memory to the non-volatile memory.

Abstract: Non-volatile memory systems such as those using NAND FLASH technology have a property that a memory location can be written to only once prior to being erased, and a contiguous group of memory locations need to be erased simultaneously. The process of recovering space that is no longer being used for storage of current data, called garbage collection, may interfere with the rapid access to data in other memory locations of the memory system during the erase period. The effects of garbage collection on system performance may be mitigated by performing portions of the process contemporaneously with the user initiated reading and writing operations. The memory circuits and the data may also be configured such that the data is stored in stripes of a RAID array and the scheduling of the erase operations may be arranged so that the erase operations for garbage collection are hidden from the user operations.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory using first data. The controller is configured to write either the first data or second data into the nonvolatile memory based on a total write amount of user data into the nonvolatile memory. The second data is compressed data of the first data.

Abstract: This document relates to data storage techniques. One example can buffer write commands and cause the write commands to be committed to storage in flush epoch order. Another example can maintain a persistent log of write commands that are arranged in the persistent log in flush epoch order. Both examples may provide a prefix consistent state in the event of a crash.

Abstract: A computer-implemented method for implementing a RAID array, according to one approach, includes: predicting a compression ratio of data to be stored in the RAID array, and using the predicted compression ratio and a physical storage capacity of the RAID array to calculate a maximum virtual storage capacity of the RAID array. The maximum virtual storage capacity is used to establish an effective storage capacity of the RAID array. One or more instructions to store compressed data in the RAID array are also sent. In response to occurrence of a predetermined event, a current compression ratio of the compressed data stored in the RAID array and the physical storage capacity of the RAID array are used to calculate a current virtual storage capacity of the RAID array. Furthermore, the effective storage capacity of the RAID array is scaled based on the current virtual storage capacity.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Abstract: Systems, apparatuses, and methods for determining preferred memory page management policies by software are disclosed. Software executing on one or more processing units generates a memory request. Software determines the preferred page management policy for the memory request based at least in part on the data access size and data access pattern of the memory request. Software conveys an indication of a preferred page management policy to a memory controller. Then, the memory controller accesses memory for the memory request using the preferred page management policy specified by software.

Abstract: Embodiments for trigger event detection for automatic log collection in an automated data storage library by a processor. A triggering event associated with the automated data storage library may be detected using firmware of the automated data storage library such that the triggering event is one from a group that includes a drive or library reset, a component action, and a service action. A snapshot of one or more logs associated with the automated data storage library may be captured upon detection of the triggering event, wherein the one or more logs include at least one of diagnostic information, statistical information, configuration information, backup information, database information, or a combination thereof. The snapshot of the one or more logs by the automated data storage library may be stored.