Abstract: Methods, systems, and computer readable media for optimizing storage of application data in memory are disclosed. According to one method for optimizing storage of application data in memory, the method includes receiving application data associated with an application. The method also includes generating, using information about the application, information about a processor, and information about a memory, a memory map indicating one or more memory locations in the memory for storing the application data. The method further includes storing, using the memory map, the application data in the one or more memory locations. The method also includes executing, using the processor, the application that uses the application data.

Abstract: An apparatus and method for tagged memory management.

Abstract: Various embodiments include methods and devices for generating a memory map configured to map virtual addresses of pages to physical addresses, in which pages of a same size are grouped into regions. The embodiments may include adding a first entry for a first additional page to a first region in the memory map, shifting virtual addresses of the first region to accommodate a shift of virtual addresses of the first region allocated for code by a sub-page granular shift amount, mapping shifted virtual addresses of the first entry for the first additional page to physical address mapped to a first lowest shifted virtually addressed page of the first region, and shifting the virtual addresses of the first region allocated for code by a sub-page granular shift amount, in which the virtual addresses of the first region allocated for code partially shift into the first entry for the first additional page.

Abstract: Several embodiments of memory devices and systems having a variable logical memory capacity are disclosed herein. In one embodiment, a memory device can include a plurality of memory regions that collectively define a physical memory capacity and a controller operably coupled to the plurality of memory regions. The controller is configured to advertise a first logical memory capacity to a host device, wherein the first logical memory capacity is less than the physical memory capacity, determine that at least one of the memory regions is at or near end of life, and in response to the determination, (1) retire the at least one of the memory regions and (2) reduce a logical memory capacity of the host device to a second logical memory capacity that is less than the first logical memory capacity.

Abstract: Devices and techniques for memory access bounds checking for a programmable atomic operator are described herein. A processor can execute a programmable atomic operator with a base memory address. The processor can obtain a memory interleave size indicator corresponding to the programmable atomic operator and calculate a contiguous memory address range from the base memory address and the memory interleave size. The processor can then detect that a memory request from the programmable atomic operator is outside the contiguous memory address range and deny the memory request when it is outside of the contiguous memory address range and allow the memory request otherwise.

Abstract: Techniques for caching may include: determining an update to a first data page of a first cache on a first node, wherein a second node includes a second cache and wherein the second cache includes a copy of the first data page; determining, in accordance with one or more criteria, whether to send the update from the first node to the second node; responsive to determining, in accordance with the one or more criteria, to send the update, sending the update from the first node to the second node; and responsive to determining not to send the update, sending an invalidate request from the first node to the second node, wherein the invalidate request instructs the second node to invalidate the copy of the first data page stored in the second cache of the second node.

Abstract: Techniques are provided for the scheduling of file pre-fetches from a file system into a cache memory, to reduce subsequent latency associated with future accesses to those files. A methodology implementing the techniques according to an embodiment includes monitoring accesses to files of the file system (e.g., file open and file read operations) and maintaining a record for each of the accessed files. The record includes an identifier of the file, the number of accesses of the file, and the number of cache memory misses associated with those accesses. The method also includes storing the record into a file access history database (FAHD). The method further includes generating, in response to an Operating System (OS) shutdown, a frequently used file list (FUFL) based on the FAHD. The method further includes pre-fetching files identified by a selected subset of the FUFL to the cache memory during an OS boot.

Abstract: System and techniques for performing selective snapshot and backup copy operations for individual virtual machines in a shared storage. The system can include a hypervisor configured to create and operate a plurality of virtual machines. The system can also include one or more shared physical computer storage devices communicatively coupled to the hypervisor to store the plurality of virtual machines. A plurality of storage volumes can be provided in the one or more shared physical computer storage devices, each storage volume uniquely corresponding to one of the virtual machines. The system can also include a virtual server agent configured to issue a command to the hypervisor to perform a snapshot or backup copy operation for a selected one of the plurality of virtual machines without performing the operation for any other unselected virtual machine in the one or more shared physical computer storage devices.

Abstract: A system includes a memory including a plurality of memory pages, a processor in communication with the memory, and a supervisor. The supervisor is configured to locate at least two duplicate memory pages of the plurality of memory pages, write-protect the at least two duplicate memory pages, and add the at least two duplicate memory pages to a list. Responsive to a first page of the at least two duplicate memory pages changing, the supervisor is configured to remove the first page from the list. Responsive to a memory pressure-triggering event, the supervisor is configured to remove a second page of the at least two duplicate memory pages from the list. The second page is reused after removal from the list.

Abstract: A system includes having buffers and a processing device that receives a read request with a logical block address (LBA) value for a memory device, creates a logical transfer unit (LTU) value, to include the LBA value, that is mapped to a first physical address of the memory device, and generates command tags that are to direct the processing device to retrieve data from the memory device and store the data in buffers. The command tags include a first command tag associated with the first physical address and a second command tag associated with a second physical address that sequentially follows the first physical address. The processor further creates an entry in the read cache table for the buffers. The entry can include a starting LBA value set to the first LBA value and the read offset value corresponding to the amount of data.

Abstract: System and methods for evicting and inserting eviction an entry for a deduplication table are described.

Abstract: Provided is a method of adjusting prefetching operations, the method including setting a prefetching distance, accessing a prefetching-trigger key, determining a target key is outside of the prefetching distance from the prefetching-trigger key, increasing the prefetching distance, and successfully fetching a subsequent target key of a subsequent prefetching-trigger key from a prefetching read-ahead buffer.

Abstract: A cache memory device includes a cache circuit and a way prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to an access address are stored in cache lines and performs a current cache access operation primarily with respect to candidate ways based on a candidate way signal indicating the candidate ways in a way prediction mode. The way prediction circuit stores accumulation information by accumulating a cache hit result indicating whether the target data are stored in one of ways and a way prediction hit result indicating whether the target data are stored in one of the candidate ways based on the cache hit signal provided during previous cache access operations. The way prediction circuit generates the candidate way signal by determining the candidate ways for the current cache access operation based on the accumulation information in the way prediction mode.

Abstract: Embodiments described herein relate to techniques for placing backup data based on health scores. The techniques may include: obtaining data items associated with a first data domain restorer; obtaining data items associated with a second data domain restorer; making a prediction that the first data domain restorer is operating normally; making a prediction that the second data domain restorer is operating normally; assigning a confidence value to the first prediction; making a classification of the first data domain restorer in a first group based on the confidence value; assigning a confidence value to the second prediction; making a classification of the second data domain restorer in a second group based on the confidence value; and performing a data backup to the first data domain restorer from a first computing device based on the classification and a first service level required for the first computing device.

Abstract: A method for characterizing workload sequentiality for cache policy optimization includes maintaining an IO trace data structure having a rolling window of IO traces describing access operations on addresses of a storage volume. A page count data structure is maintained that includes a list of all of the addresses of the storage volume referenced by the IO traces in the IO trace data structure. A list of sequences data structure is maintained that contains a list of all sequences of the addresses of the storage volume that were accessed by the IO traces in the IO trace data structure. A sequence lengths data structure is used to correlate each sequence in the list of sequences data structure with a length of the sequence, and a histogram data structure is used to correlate sequence lengths and a number of how many of sequences of each length are maintained in the sequence lengths data structure.

Abstract: An analysis device configured to be connected to an information processing apparatus configured to mount a first memory and a low-speed second memory, the low-speed second memory being cheaper and having lower performance than the first memory and being used for memory capacity expansion, the analysis device being configured to perform program instructions including: causing the information processing apparatus to execute a plurality of types of performance evaluation application programs and acquire memory performance characteristic information regarding each performance evaluation application program from the information processing apparatus; determining a recommended memory configuration according to the performance evaluation application program corresponding to the application to be evaluated program among the plurality of types of performance evaluation application programs by using a collection result of the memory performance characteristic information; and outputting recommended memory configuration

Abstract: A memory controller includes a read only memory (ROM) suitable for outputting a ROM code to execute firmware in response to fuse data and a control processor suitable for executing the firmware in response to the ROM code. A memory system includes the memory controller and a storage device storing data.

Abstract: Remote copy operations are performed to copy data from a primary storage controller to a secondary storage controller, wherein input/output (I/O) requests are received at the primary storage controller from a host both via a bus interface and a network interface while the remote copy operations are in progress, and wherein consistency groups are formed during the remote copy operations to copy the data consistently. Quiescing of I/O operations performed via the bus interface are performed while a current consistency group is being replaced by a next consistency group during the remote copy operations.

Abstract: An operating method of a memory system that includes a memory device including a plurality of blocks and a controller including a memory in which a first open block list and a second open block list are stored, the method comprising receiving a write request and a logical address from a host; converting the logical address into a first virtual address; converting the first virtual address into a physical address; performing a first error checking operation of checking a mapping relationship between the first virtual address and the physical address based on the first open block list; performing a second error checking operation of checking whether the physical address is included in the second open block list; and performing a write operation on an open block corresponding to the physical address when it is determined that the physical address is not allocated more than once.

Abstract: Translation lookaside buffer (TLB) invalidation using virtual addresses is provided. A cache is searched for a virtual address matching the input virtual address. Based on a matching virtual address in the cache, the corresponding cache entry is invalidated. The load/store queue is searched for a set and a way corresponding to the set and the way of the invalidated cache entry. Based on an entry in the load/store queue matching the set and the way of the invalidated cache entry, the entry in the load/store queue is marked as pending. Indicating a completion of the TLB invalidate instruction is delayed until all pending entries in the load/store queues are complete.