Field effect transistor including strained germanium fins
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.
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The present disclosure relates generally to semiconductor devices and relates more specifically to multiple gate field effect transistors.
BACKGROUND OF THE DISCLOSUREMultiple gate field effect transistors (FETs) are metal-oxide-semiconductor field effect transistors (MOSFETs) that incorporate more than one gate into a single device. A finFET is a specific type of multiple gate FET in which the conducting channel is wrapped by a thin fin forming the body of the device. The effective channel length of the device in this case is determined by the thickness of the fin (measured from source to drain). The wrap-around structure of the gate provides improved electrical control over the channel, and thus helps mitigate leakage current and other short-channel effects.
SUMMARY OF THE DISCLOSUREIn one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium. For example, the at least one fin of the p-type field effect transistor region may include compressive strained germanium, while the at least one fin of the n-type field effect transistor region may include tensile strained germanium.
In another example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes a first mandrel including relaxed silicon germanium and a first fin grown on a sidewall of the mandrel. The first fin includes compressive strained germanium. The n-type field effect transistor region includes a second mandrel including at least one relaxed Group III-V semiconductor material and a second fin grown on a sidewall of the second mandrel. The second fin includes tensile strained germanium.
In another example, a method for fabricating a device includes forming a first mandrel in a p-type field effect transistor region of the device and forming a second mandrel in an n-type field effect transistor region of the device. A first compressive strained germanium fin is grown on a sidewall of the first mandrel, and a second tensile strained germanium fin is grown on a sidewall of the second mandrel.
The teachings of the present disclosure can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:
To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the Figures.
DETAILED DESCRIPTIONIn one example, a field effect transistor including strained germanium fins is disclosed. When used in the fins of a p-type FET (pFET), germanium has been experimentally and theoretically shown to offer higher carrier (hole) mobility and improved capacity for inversion layer thickness (Tinv) scaling relative to conventional silicon. However, when used in the fins of an n-type FET (nFET), the improvements in carrier (electron) mobility and Tinv scaling are less pronounced. Using Groups III-V semiconductor materials in the fins can improve carrier mobility in the nFET, but low density of states effective mass of these materials makes Tinv scaling more difficult.
Examples of the present disclosure provide a finFET including strained germanium fins in both the pFET and nFET regions. In one particular example, the fins in the pFET region include compressive strained germanium, while the fins in the nFET region include tensile strained germanium. A fabrication process for the disclosed finFET includes growing the strained germanium on sidewalls of dummy mandrels, which may be formed from relaxed Groups III-IV semiconductor materials and/or relaxed silicon germanium (SiGe). Homo-integration of the pFET and nFET regions via this fabrication process allows the thermal budgets to match the first order. The strained germanium in the nFET region improves carrier mobility relative to silicon, while the Tinv can be scaled to sub-one nanometer, resulting in better electrostatics and relaxing the need for fin width shrinkage for a given gate length.
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In a different example (e.g., where the mandrels were recessed to the depth of the germanium containing layers 124 or deeper in
Front end of line (FEOL) high-k metal gate (HK/MG) integration can proceed from the point illustrated in
Although various embodiments which incorporate the teachings of the present invention have been shown and described in detail herein, those skilled in the art can readily devise many other varied embodiments that still incorporate these teachings.
Claims
1. A device comprising:
- a p-type field effect transistor region including a first fin comprising compressive strained germanium grown on a first mandrel, wherein the first mandrel is recessed to a depth below a first end of the first fin; and
- an n-type field effect transistor region including a second fin comprising tensile strained germanium grown on a second mandrel, wherein the second mandrel is recessed to a depth below a first end of the second fin.
2. The device of claim 1, wherein the first mandrel comprises silicon germanium.
3. The device of claim 2, wherein the silicon germanium is strain relaxed silicon germanium.
4. The device of claim 3, wherein a second end of the first fin is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the second end of the first fin directly contact the shallow trench isolation layer.
5. The device of claim 4, wherein a second side of the second end of the first fin includes a lower portion that directly contacts the relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer.
6. The device of claim 1, wherein the second mandrel comprises a Group III-V semiconductor material.
7. The device of claim 6, wherein the Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
8. The device of claim 7, wherein a second end of the second fin is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the second end directly contact the shallow trench isolation layer.
9. The device of claim 8, wherein a second side of the second end of the second fin includes a lower portion that directly contacts the strain relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
10. The device of claim 6, wherein the Group III-V semiconductor material comprises:
- a layer of gallium arsenide; and
- a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
11. A device comprising:
- a p-type field effect transistor region, comprising: a first mandrel comprising relaxed silicon germanium; and a first fin grown on a sidewall of the first mandrel and comprising compressive strained germanium, wherein the first mandrel is recessed to a depth below a first end of the first fin; and
- an n-type field effect transistor region, comprising: a second mandrel comprising at least one relaxed Group III-V semiconductor material; and a second fin grown on a sidewall of the second mandrel and comprising tensile strained germanium, wherein the second mandrel is recessed to a depth below a first end of the second fin.
12. The device of claim 11, wherein the first fin comprises:
- a second end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the second end directly contact the shallow trench isolation layer, and a second side of the second end includes a lower portion that directly contacts the relaxed silicon germanium and an upper portion that directly contacts the shallow trench isolation layer.
13. The device of claim 11, wherein the second fin comprises:
- a second end that is buried in a shallow trench isolation layer of the device, such that a bottom and a first side of the second end directly contact the shallow trench isolation layer, and a second side of the second end includes a lower portion that directly contacts the relaxed Group III-V semiconductor material and an upper portion that directly contacts the shallow trench isolation layer.
14. A method for fabricating a device, the method comprising:
- forming a first mandrel in a p-type field effect transistor region of the device;
- forming a second mandrel in an n-type field effect transistor region of the device;
- growing a compressive strained germanium fin on a sidewall of the first mandrel;
- recessing the first mandrel to a depth below a first end of the compressive strained germanium fin;
- growing a tensile strained germanium fin on a sidewall of the second mandrel; and
- recessing the second mandrel to a depth below a first end of the tensile strained germanium fin.
15. The method of claim 14, wherein the first mandrel and the second mandrel are formed using aspect ratio trapping.
16. The method of claim 14, wherein the first mandrel comprises silicon germanium.
17. The method of claim 16, wherein the silicon germanium is strain relaxed silicon germanium.
18. The method of claim 14, wherein the second mandrel comprises at least one Group III-V semiconductor material.
19. The method of claim 18, wherein the at least one Group III-V semiconductor material is a strain relaxed Group III-V semiconductor material.
20. The method of claim 19, wherein the at least one Group III-V semiconductor material comprises:
- a layer of gallium arsenide; and
- a layer of indium gallium arsenide deposited over the layer of gallium arsenide.
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Type: Grant
Filed: Nov 16, 2016
Date of Patent: Apr 24, 2018
Patent Publication Number: 20170148680
Assignee: International Business Machines Corporation (Armonk, NY)
Inventors: Karthik Balakrishnan (White Plains, NY), Kangguo Cheng (Schenectady, NY), Pouya Hashemi (White Plains, NY), Alexander Reznicek (Troy, NY)
Primary Examiner: Benjamin Sandvik
Assistant Examiner: Gustavo Ramallo
Application Number: 15/353,022
International Classification: H01L 29/78 (20060101); H01L 21/02 (20060101); H01L 27/092 (20060101); H01L 21/8258 (20060101); H01L 21/8238 (20060101); H01L 21/8252 (20060101);