Abstract: A method and apparatus for hybrid automatic retransmission request (HARQ) is provided. The method is performed by a first UE. The method includes receiving, from a NodeB, an acknowledge configuration indicating an HARQ scheme of the first UE and uplink resource for the HARQ scheme; determining whether an acknowledgement for a data block associated with a first downlink control information (DCI) is to be transmitted according to the HARQ scheme.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a reference signal for estimation of at least one parameter associated with generation of an adapted low density parity check (LDPC) graph. The UE may transmit an indication of an adapted LDPC graph that is based on at least one adaptation metric associated with the at least one parameter. The UE may receive, based on the adapted LDPC graph, a downlink shared channel communication. Numerous other aspects are described.

Abstract: The present disclosure relates to a memory device comprising an array of memory cells and an operating circuit for managing the operation of the array, the operating circuit comprising an encoding unit configured to generate a codeword, the codeword comprising payload data stored in a plurality of memory cells of the array, parity data associated with the payload data stored in parity cells of the memory array, wherein a number of parity cells to be used to store the parity data is selectable based on a status of the plurality of memory cells and is related to a selected Error Correction Code (ECC) protection level, and extra payload data stored in unused parity cells, the device further comprising a decoding unit configured to perform an ECC operation on the stored codeword based on the selected ECC protection level.

Abstract: A storage device may include a memory device and a memory controller. The memory device may store data. The memory controller may iterate error correction decoding on data read from the memory device, determine whether to continue iterating based on a result obtained by comparing a first threshold number with a number of Unsatisfied Check Nodes (UCNs) included in a syndrome of first decoded data, which is a result of a first set number of iterations of the error correction decoding on the read data, and determine whether to continue iterating based on a result obtained by comparing a second threshold number with a number of UCNs included in a syndrome of second decoded data, which is a result of a sum of the first set number and a second set number of iterations of the error correction decoding on the read data.

Abstract: According to various embodiments, an electronic device comprises: at least one processor; and memory operatively connected to the at least one processor, wherein the memory may store instructions which, when executed by the at least one processor, cause the electronic device to: obtain, from a kernel, at least one address for a first memory area accessible through the kernel; store the at least one address in a second memory area accessible through a hypervisor; based on obtaining an address stored in a kernel stack from the kernel, identify whether the obtained address is defective, on the basis of the at least one stored address; and restore the defective address using at least one address stored in the second memory area in response to identifying the defect in the address.

Abstract: Embodiments of the present disclosure include techniques for predictive memory maintenance. In one embodiment, locations of correctable errors in a memory are observed. A machine learning (ML) system may be trained with patterns of correctable errors that result in uncorrectable errors. A trained ML monitors correctable errors to predict when memory requires maintenance. In another embodiment, error rates from multiple memories are monitored to predict memory channel and other upstream device failures.

Abstract: Systems and methods are described herein that allow information carrying bits of a transmission block to be placed at higher-reliability positions prior to transmission. An exemplary method includes generating a set of payload bits to be encoded for transmission, wherein the set of payload bits includes at least one known bit, interleaving the set of payload bits to generate an interleaved set of payload bits, wherein the interleaved set includes the at least one known bit in a predetermined position in the interleaved set, providing the interleaved set to a cyclic redundancy check (CRC) encoder to generate CRC-interleaved set of payload bits, wherein the CRC-interleaved set includes the at least one known bit in a predetermined position within the CRC-interleaved set, and encoding the CRC-interleaved set for transmission to a wireless device. Associated network nodes and wireless devices are included.

Abstract: The technology described herein includes a first plurality of bijection diffusion function circuits to diffuse data bits into diffused data bits and store the diffused data bits into a memory; an error correcting code (ECC) generation circuit to generate ECC bits for the data bits; and a second plurality of bijection diffusion function circuits to diffuse the ECC bits into diffused ECC bits and store the diffused ECC bits into the memory.

Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

Abstract: A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

Abstract: Systems and techniques that facilitate Stark shift cancellation are provided. In various embodiments, a system can comprise a control qubit that is coupled to a target qubit. In various cases, the control qubit can be driven by a first tone that entangles the control qubit with the target qubit. In various aspects, the control qubit can be further driven by a second tone simultaneously with the first tone. In various cases, the second tone can have an opposite detuning sign than the first tone. In various instances, the first tone can cause a Stark shift in an operational frequency of the control qubit, and the second tone can cancel the Stark shift.

Abstract: After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Abstract: Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.

Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X?1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

Abstract: According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Abstract: A method for compressing a signal, the method comprising: acquiring, via a signal recording module, a primary signal; modelling, via a processor, a model signal of the primary signal by: acquiring, via the processor, a sampled signal; acquiring, via the processor, a windowed signal; and extracting, via the processor: a fundamental frequency waveform having a fundamental magnitude and a fundamental phase; and at least one harmonic frequency waveform having a harmonic magnitude and a harmonic phase; wherein the model signal comprises the fundamental frequency waveform and the at least one harmonic frequency waveform; calculating, via the processor, an error signal between a reconstructed signal and the primary signal; determining, via the processor, an optimal gain from at least; an averaging step providing an average value, a predefined threshold, and a scaled signal.

Abstract: A processing-in-memory (PIM) device includes a data register configured to store reference value data, and a multiplication/accumulation (MAC) operator configured to perform a comparison operation, a multiplication operation, and an addition operation on first data and second data, based on the reference value data to generate MAC operation result data when a MAC operation is performed.