Patents Examined by Guy J. Lamarre
  • Patent number: 11928354
    Abstract: A read-disturb-based read temperature determination system includes a storage device that is coupled to a read temperature adjustment subsystem. The storage device receives data from the read temperature adjustment subsystem, stores the data in a block in the storage device, identifies read disturb information for a row in the block at a plurality of different times, processes the read disturb information to generate a read temperature for the row, provides the read temperature in a local logical storage element read temperature map and, based on instructions from the read temperature adjustment subsystem, adjusts the read temperature provided in the local logical storage element read temperature map.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Ali Aiouaz, Walter A. O'Brien, III, Leland W. Thompson
  • Patent number: 11928026
    Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.
    Type: Grant
    Filed: February 27, 2023
    Date of Patent: March 12, 2024
    Assignee: SK hynix Inc.
    Inventors: Munseon Jang, Hoi Ju Chung, Jang Ryul Kim
  • Patent number: 11921579
    Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: March 5, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ki-Heung Kim, Jun Hyung Kim, Chang-Yong Lee, Sang Uhn Cha, Kyung-Soo Ha
  • Patent number: 11922046
    Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.
    Type: Grant
    Filed: March 10, 2023
    Date of Patent: March 5, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Brian T. Gold, Ronald Karr
  • Patent number: 11914471
    Abstract: Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.
    Type: Grant
    Filed: August 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Sanjay Subbarao
  • Patent number: 11914469
    Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: February 27, 2024
    Assignee: VMware, Inc.
    Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
  • Patent number: 11907065
    Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.
    Type: Grant
    Filed: January 25, 2023
    Date of Patent: February 20, 2024
    Assignee: VMware, Inc.
    Inventors: Marcos K. Aguilera, Keerthi Kumar, Pramod Kumar, Pratap Subrahmanyam, Sairam Veeraswamy, Rajesh Venkatasubramanian
  • Patent number: 11907064
    Abstract: A memory controller includes a fault predictor which predicts a fault which causes an error occurring in a memory device, an error correction code (ECC) manager which classifies a type of the fault based on the predicted fault, and a plurality of ECC engines which perform ECC in parallel depending on the classified type of the faults. The fault predictor includes a memory error profiler which receives raw data related to the error and processes the raw data into an error profile that is data available for machine learning, and a memory fault prediction network which receives the error profile as an input, performs the machine learning using the error profile, and predicts the fault which causes the error.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: February 20, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Youn Kim, Su Hun Lim
  • Patent number: 11907808
    Abstract: Apparatus and method for measurement-free (MF) quantum error correction (QEC). For example, one embodiment of a method comprises: determining an error syndrome on a first subset of ancilla qubits of a quantum processor; decoding the error syndrome to produce decoded results on a second subset of ancilla qubits of the quantum processor; applying the decoded results to one or more system qubits; and unconditionally resetting the first subset and/or second subset of ancilla qubits to remove entropy and/or noise from the quantum system, wherein the operations of determining the error syndrome, decoding the error syndrome, applying the error syndrome, and unconditionally resetting the first and/or second subset of ancilla qubits are performed responsive to a qubit controller executing quantum control instructions provided from or derived from a script and without transmitting measurement data related to the error syndrome to a non-quantum computing device.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: February 20, 2024
    Assignee: Intel Corporation
    Inventors: Albert Schmitz, Anne Matsuura, Ravi Pillarisetty, Shavindra Premaratne, Justin Hogaboam, Lester Lampert
  • Patent number: 11900212
    Abstract: In a general aspect, a quantum process for execution by a quantum processor is generated. In some instances, test data representing a test output of a quantum process are obtained. The test data are obtained based on a value assigned to a variable parameter of the quantum process. An objective function is evaluated based on the test data, and an updated value is assigned to the variable parameter based on the evaluation of the objective function. The quantum process is provided for execution by a quantum processor, and the quantum process provided for execution has the updated value assigned to the variable parameter.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: February 13, 2024
    Assignee: Rigetti & Co, LLC
    Inventors: William J. Zeng, Chad Tyler Rigetti
  • Patent number: 11894927
    Abstract: A data transmission method and device are provided. The method includes: generating a first physical layer protocol data frame, where the first physical layer protocol data frame includes a first identification bit and a second identification bit, the first identification bit is used for identifying whether the first physical layer protocol data frame is a retransmission data frame, and the second identification bit is used for identifying the number of retransmissions of the first physical layer protocol data frame; and sending the first physical layer protocol data frame.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: February 6, 2024
    Assignee: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventor: Xiandong Dong
  • Patent number: 11893018
    Abstract: A computing system is operable to generate a plurality of lines of coding blocks that includes a plurality of data blocks and a plurality of parity blocks. Each of the plurality of lines of coding blocks includes a corresponding subset of data blocks a corresponding subset of parity blocks. A set of segments of a segment group are generated to collectively include the plurality of lines of coding blocks. Different coding blocks of each of the plurality of lines of coding blocks are included within different ones of the set of segments, and the plurality of parity blocks are dispersed across all of the set of segments. The set of segments are stored via a plurality of nodes sets, where different segments of the set of segments are stored via memory resources of different node sets of the plurality of node sets.
    Type: Grant
    Filed: February 8, 2023
    Date of Patent: February 6, 2024
    Assignee: Ocient Inc.
    Inventors: George Kondiles, Jason Arnold
  • Patent number: 11893284
    Abstract: The present disclosure provides a method, device and system for testing memory devices. The testing method includes: receiving a test instruction, the test instruction being used to characterize a model of a memory device to be tested that is connected to a test platform; selecting, according to the test instruction, a testing method corresponding to the model of the memory device to be tested from a plurality of pre-stored testing methods as a target testing method; and executing the target testing method to test the memory device to be tested.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: February 6, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Xinwang Chen, Maosong Ma, Jianbin Liu
  • Patent number: 11886289
    Abstract: A display device includes an external memory device which stores a first integrated circuit (“IC”) driving information, an internal memory device which stores a second IC driving information generated by copying the first IC driving information, a buffer which receives the second IC driving information and detects an electrostatic discharge current, an error correction code calculator which determines a first error correction code of the first IC driving information and a second error correction code of the second IC driving information when the electrostatic discharge current is detected, and an error correction code comparator which compares the first error correction code and the second error correction code. The internal memory device selectively updates the second IC driving information to the first IC driving information based on a result of a comparison of the first error correction code and the second error correction code.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: January 30, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Sang Kuk Kim
  • Patent number: 11886292
    Abstract: Provided is a memory system, which includes: a memory, configured to, during a read or write operation, write or read multiple data, the multiple data are divided into M bytes, each having N data; and an encoding module, configured to generate, at an encoding stage, X first check codes, each based on a subset of the data at fixed bits among all the bytes, and to generate, at the encoding stage, Y second check codes based on all data in a subset of the bytes, the X first check codes are configured for at least one of error detection or error correction on the N data in each of the bytes, and the Y second check codes are configured for at least one of error detection or error correction on the M bytes.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: January 30, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventor: Kangling Ji
  • Patent number: 11874738
    Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: January 16, 2024
    Assignee: Kioxia Cororation
    Inventors: Noboru Okamoto, Toshikatsu Hida
  • Patent number: 11874737
    Abstract: A selecting bad data column method suitable for a data storage device is provided. The data storage device includes a control unit and a data storage medium. The selecting method performed by the control unit includes: reading written data of each data column as read data; comparing the read data and the written data of each data column to calculate an average number of error bits of each data column; determining whether the average number of error bits of each data column is greater than or equal to a predetermined value; and recording a data column as a bad data column when the average number of error bits of the data column is greater than or equal to the predetermined value. In this way, in order to avoid the problems that the error correction code can't be corrected or the correction capability is excessively consumed.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: January 16, 2024
    Assignee: Silicon Motion, Inc.
    Inventor: Sheng-Yuan Huang
  • Patent number: 11868211
    Abstract: The present disclosure includes apparatuses, methods, and systems for error detection and correction in memory. An embodiment includes a memory having a group of self-selecting memory cells which store data corresponding to a codeword from an error correcting code, and circuitry configured to perform a sense operation on the group of self-selecting memory cells, identify, based on the sense operation, memory cells of the group that cannot store data, mark data sensed from the identified memory cells as erasures and perform an error correction operation on data sensed from the group of self-selecting memory cells with the data sensed from the identified memory cells marked as erasures.
    Type: Grant
    Filed: September 26, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Joseph M. McCrate, Robert J. Gleixner
  • Patent number: 11870463
    Abstract: Systems, methods, and apparatus related to memory devices such as solid state drives. In one approach, data is received from a host system (e.g., data to be written to an SSD). The received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of a storage device (e.g., the SSD) will store the received data is determined. In response to determining the temperature, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The identified first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells of the storage device.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: January 9, 2024
    Assignee: Lodestar Licensing Group LLC
    Inventors: Poorna Kale, Christopher Joseph Bueb
  • Patent number: 11863544
    Abstract: A method authenticates nodes in a communication network of an automation installation. Respective authentication information is transmitted to an authentication server, which takes the authentication information as a basis for admitting or rejecting the nodes in the communication network as subscribers. In order to be able to perform an authentication of a node even in a communication network configured with redundancy, the communication network contains multiple nodes, each of which has at least two communication ports. The communication network executes a spanning tree protocol and at least two of the nodes use their mutually facing communication ports to interchange authentication requests and send the respective received authentication information to an authentication server, connected to the communication network, that uses the respective received authentication information to perform a check on the authenticity of the node and admits or rejects the node in the communication network based on the check.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: January 2, 2024
    Assignee: Siemens Aktiengesellschaft
    Inventors: Andrej Goerbing, Jonas Hurrelmann