Abstract: A processing-in-memory (PIM) device includes a data register configured to store reference value data, and a multiplication/accumulation (MAC) operator configured to perform a comparison operation, a multiplication operation, and an addition operation on first data and second data, based on the reference value data to generate MAC operation result data when a MAC operation is performed.

Abstract: A method may comprise receiving a first signal comprising first LDPC bits including systematic bits and parity bits and transmitting information indicating that the first signal was incorrectly received. A second signal comprising second LDPC bits may be received in response to the transmitting. The second signal may include LDPC bits according to a lifting size of an LDPC base graph.

Abstract: A storage device includes a non-volatile memory device that includes memory blocks each including one or more memory cells, a combo integrated circuit (IC) that includes a temperature sensor and a memory, and a controller that is connected with the combo IC through first channels and controls the non-volatile memory device to write or read data in or from selected memory cells. When the controller determines that a first event occurs based on temperature data read from the combo IC, the controller records first event data in the memory of the combo IC. In a first operation mode, the combo IC outputs the first event data to the controller through the first channels. In a second operation mode, under control of an external host, the combo IC outputs the first event data to the external host through second channels different from the first channels.

Abstract: A computing system is operable to generate a first plurality of lines of coding blocks that includes a first plurality of data blocks and a first plurality of parity blocks. A first set of segments of a first segment group that collectively include the first plurality of lines of coding blocks are generated, and the first set of segments of the first segment group are stored via a first plurality of computing devices of a first storage cluster of the computing system. A second plurality of lines of coding blocks that includes a second plurality of data blocks and a second plurality of parity blocks are generated. A second set of segments of a second segment group that collectively include the second plurality of lines of coding blocks are generated. The second set of segments of the second segment group are stored via a second plurality of computing devices of a second storage cluster of the computing system.

Abstract: Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry.

Abstract: An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.

Abstract: An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate write data and a write fail check signal from write input data when a write operation in an operation mode is performed, and generate a fail flag signal and converted data from read data and a read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data, based on the fail flag signal to generate MAC operation result data.

Abstract: The Fleetwide Adaptive Rate Limiting Gatekeeper Apparatuses, Processes and Systems (“FARLG”) transforms API call permission request, API call result request datastructure/inputs via FARLG components into API call permission response, API call result response outputs. An API call permission request datastructure associated with an API call of an application structured to identify an API and a set of scopes is obtained. A retry-after interval is determined for each scope in the set of scopes, in which existence of a retry-after interval for a scope indicates that the API previously returned a throttled response for the scope. A wait duration associated with the API call is determined as the maximum retry-after interval across retry-after intervals that exist for the set of scopes. An API call permission response datastructure structured to specify the wait duration is provided.

Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

Abstract: Separate inter-die connectors for data and error correction information and related apparatuses, methods, and computing systems are disclosed. An apparatus including a master die, a target die, inter-die data connectors, and inter-die error correction connectors. The target die includes data storage elements. The inter-die data connectors electrically couple the master die to the target die. The inter-die data connectors are configured to conduct write data bits from the master die to the target die. The write data bits are written to the data storage elements. The inter-die error correction connectors electrically couple the master die to the target die. The inter-die error correction connectors are configured to conduct error correction information corresponding to the write data bits from the master die to the target die. The target die includes error correction circuitry configured to generate new error correction information responsive to the write data bits received from the master die.

Abstract: Methods, systems, and devices for error status determination at a memory device are described. A memory device may generate, based on syndrome bits for a codeword read from a memory, an error detection signal for the codeword that indicates whether an error has been detected in the codeword. The memory device may generate, based on the syndrome bits, an error correction signal for the codeword that indicates whether an error has been corrected in the codeword. And the memory device may provide an indication of the error detection signal and an indication of the error correction signal to a host device.

Abstract: Systems and methods for operating one or more qubits in a quantum computing system are provided. In some examples, a method can include obtaining past time data associated with a temporal metric of an operating parameter of a qubit in a quantum device. The method can include selecting an operating parameter value based at least in part on the past time data associated with the temporal metric of the operating parameter to reduce likelihood of occurrence of a time dependent defect. The time dependent defect can exhibit a time dependent behavior. The method can include operating the qubit in the quantum device at the operating parameter value.

Abstract: A storage network operates by: receiving a encoded data slice for storage by the storage network, wherein the encoded data slice is associated with a vault; generating a encryption key corresponding to the encoded data slice based on a vault identifier associated with the vault; utilizing the encryption key to generate a encrypted data slice and that corresponds to, and is based on, the encoded data slice; storing the encrypted data slice in a storage unit of the storage network; receiving a request to retrieve the encoded data slice; retrieving the encrypted data slice corresponding to the encoded data slice from the storage unit of the storage network; generating a decryption key corresponding to the encoded data slice based on the vault identifier, wherein the decryption key is different from the encryption key; and regenerating the encoded data slice using the decryption key.

Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

Abstract: Error correcting memory systems and methods of operating the memory systems are disclosed. In some embodiments, a memory system includes: a data memory; an ECC memory; and a data scrubbing circuit electrically coupled to the ECC memory and the data memory. The data scrubbing circuit may be configured to, in response to receiving a scrub data command, correct an error in the data memory. A code word length used to correct the error may be longer than a word length used during normal access of the data memory. In some embodiments, a memory system includes a first memory circuit associated with a first bit error rate and a second memory circuit associated with a second bit error rate. In some embodiments, a memory system includes an error correctable multi-level cell (MLC) array.

Abstract: Aspects of this technical solution can include selecting a plurality of memory locations at a memory device, the memory locations corresponding to a first page including a first plurality of bits and a second page including a second plurality of bits, modifying, based on the first plurality of bits and the second plurality of bits, a first voltage threshold corresponding to an estimated read voltage for the first plurality of bits, allocating, to a voltage range bounded by the first voltage threshold, a log-likelihood ratio (LLR), and decoding, based on the LLR corresponding to the voltage range, the first plurality of bits.

Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.