Patents Examined by Guy J. Lamarre
  • Patent number: 11562794
    Abstract: Provided is a storage device that performs a read operation by using a time interleaved sampling page buffer. The storage device controls a sensing point in time, when bit lines of even page buffer circuits are sensed, and a sensing point in time, when bit lines of odd page buffer circuits are sensed, with a certain time difference, and performs an Even Odd Sensing (EOS) operation in a stated order of even sensing and odd sensing. The storage device performs a two-step EOS operation and performs a main sensing operation on a selected memory cell according to a result of the two-step EOS operation.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: January 24, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jisu Kim, Hyunggon Kim, Sangsoo Park, Joonsuc Jang, Minseok Kim
  • Patent number: 11561854
    Abstract: A memory system connectable to a host, includes a non-volatile memory including a plurality of memory cell transistors and a controller configured to execute read operations on the non-volatile memory. The controller executes one or more first read operations on the non-volatile memory to obtain read data using read voltages that are determined from one of a plurality of entries stored in a shift table, and performs error correction on the read data, until the error correction is successful, and when the error correction on the read data is successful, records an index corresponding to the entry stored in the shift table that was used in obtaining the successfully error-corrected read data. The controller executes a second read operation on the non-volatile memory to obtain read data using read voltages that are determined from the entry stored in the shift table corresponding to the recorded index.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 24, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Noboru Okamoto, Toshikatsu Hida
  • Patent number: 11562282
    Abstract: In methods for simulating the evolution of a real-world quantum system over time, a state-preparation sequence of quantum gates is applied to a qubit register of a quantum computer. The state-preparation sequence is configured to prepare in the qubit register an initial model state representing an initial state of the real-world quantum system. A Hamiltonian operator for the real-world quantum system is received and used in the example method. The Hamiltonian operator represents two-body potential-energy interactions in a factorized form comprising at least one Majorana operator. A time-evolution-operator sequence of quantum gates comprising a block-encoded form of the Hamiltonian operator is now applied to the qubit register of the quantum computer, yielding a changed model state that represents a time-evolved state of the real-world quantum system. A measurement operation is applied subsequently to the qubit register.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: January 24, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Guang Hao Low
  • Patent number: 11557348
    Abstract: Storage devices include a memory array comprised of a plurality of memory devices arranged in word lines. The word lines are further arranged within memory blocks. When erasing memory blocks, various storage devices may utilize a stripe-erase process that alternates the erasure of word lines within the memory blocks. The stripe-erase process is often carried out in multiple steps. However, an ungraceful shutdown can interrupt the erasing processing between one of these stripe-erase steps. The status of each memory device associated with the aborted erasure needs to be known before operations can continue. Methods and systems described herein properly classify and process memory blocks after an aborted erase command by analyzing both even and odd word lines within each of the memory blocks. By properly categorizing each memory block, overprogramming and other negative effects can be avoided, increasing the overall lifespan of the storage device that utilizes a stripe-erase process.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: January 17, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Vinayak Bhat, Amiya Banerjee, Shrinidhi Kulkarni
  • Patent number: 11556415
    Abstract: A memory device may determine cell count information from a threshold voltage distribution of memory cells and may determine a detection case based on the cell count information when an error in read data, received from the memory device performing a read operation is not corrected. A memory controller may control the memory device to execute a read operation using a development time determined in consideration of an offset voltage of a read voltage corresponding to the detection case. When an error in the read data is successfully corrected, the memory controller may update a table, stored in the memory controller, using a dynamic offset voltage obtained by inputting the cell count information to a machine learning model.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sehwan Park, Jinyoung Kim, Ilhan Park, Youngdeok Seo
  • Patent number: 11550657
    Abstract: A storage apparatus includes an interface and storage circuitry. The interface communicates with a plurality of memory cells, and an individual one of the plurality of memory cells stores data in multiple programming levels. The storage circuitry configured to program data to a first group of multiple memory cells in a number of programming levels larger than two, using a One-Pass Programming (OPP) scheme that results in a first readout reliability level. After programming the data, the storage circuitry is further configured to read the data from the first group, and program the data read from the first group to a second group of the memory cells, in a number of programming levels larger than two, using a Multi-Pass Programming (MPP) scheme that results in a second readout reliability higher than the first reliability level, and reading the data from the second group of the memory cells.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: January 10, 2023
    Assignee: APPLE INC.
    Inventors: Assaf Shappir, Itay Sagron
  • Patent number: 11544010
    Abstract: An exemplary semiconductor device includes an input/output (I/O) circuit configured to combine data corresponding to a write command received via data terminals with a first subset of corrected read data retrieved from a memory cell array to provide write data. The exemplary semiconductor device further includes a write driver circuit configured to mask a write operation of a first bit of the write data that corresponds to a bit of the first subset of the read data and to perform a write operation for a second bit of the write data that corresponds to the data received via the data terminals.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Yuan He, Ming-Bo Liu
  • Patent number: 11545999
    Abstract: A data storage system and method are provided for storing data in non-volatile memory devices. Binary data is received for storage in a non-volatile memory device. The binary data is converted into non-binary data comprising base-X values, where X is an integer greater than two. The non-binary data is encoded to generate a codeword and the codeword is written to a wordline of the non-volatile memory device.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: January 3, 2023
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Richard Leo Galbraith, Jonas Andrew Goode, Niranjay Ravindran
  • Patent number: 11537468
    Abstract: In some examples, a system records, in a data structure stored in a non-volatile storage, information of memory errors in respective segments of a memory. The system determines whether memory errors of a subset of the segments satisfy a criterion, and in response to determining that the memory errors of the subset of the segments satisfy the criterion, the system groups the memory errors of the subset into a partition having a size greater than a size of a segment. The system records, in the data structure, information of memory errors in the partition, and in response to a restart of the system, retrieves the data structure from the non-volatile storage for use in an operation that addresses memory errors in the system.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: December 27, 2022
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Debdipta Ghosh, Renganathan Meenakshisundaram
  • Patent number: 11538532
    Abstract: Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: December 27, 2022
    Assignee: SILICON STORAGE TECHNOLOGY, INC.
    Inventors: Xian Liu, Chunming Wang, Nhan Do, Hieu Van Tran
  • Patent number: 11528038
    Abstract: A method and apparatus for content aware decoding utilizes a pool of decoders shared data statistics. Each decoder generates statistical data of content it decodes and provides these statistics to a joint statistics pool. As codewords arrive at the decoder pool, the joint statistics are utilized to estimate or predict any corrupted or missing bit values. Codewords may be assigned to a specific decoder, such as a tier 1 decoder, a tier 2 decoder, or a tier 3 decoder, based on a syndrome weight or a bit error rate. The assigned decoder updates the joint statistics pool after processing the codeword. In some embodiments, each decoder may additionally maintain local statistics regarding codewords, and use the local statistics when there is a statistically significant mismatch between the local statistics and the joint statistics pool.
    Type: Grant
    Filed: March 24, 2021
    Date of Patent: December 13, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy David Avraham, Ran Zamir, Omer Fainzilber
  • Patent number: 11526395
    Abstract: A read operation to retrieve data stored at a memory device is performed. Whether the data retrieved from the memory device includes an error that is not correctable is determined. Responsive to determining that the data retrieved from the memory device comprises the error that is not correctable, a buffer in a data path along which a write operation was performed to write the data at the memory device is searched for the data.
    Type: Grant
    Filed: November 20, 2020
    Date of Patent: December 13, 2022
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Wei Wang, Jiangli Zhu, Ying Yu Tai, Ning Chen, Zhengang Chen, Cheng Yuan Wu
  • Patent number: 11522559
    Abstract: Devices and techniques for variable read throughput control in a storage device are described herein. Bits from can be received for a read that is one of several types assigned to reads. A low-density parity-check (LDPC) iteration maximum can be set based on the type. LDPC iterations can be performed up to the LDPC iteration maximum and a read failure signaled in response to the LDPC iterations reaching the LDPC iteration maximum.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 6, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Xiangang Luo, Ting Luo
  • Patent number: 11520854
    Abstract: A first group of elements is element-wise multiplied with a second group of elements using a plurality of multipliers belonging to a matrix multiplication hardware unit. Results of the plurality of multipliers are added together using a hierarchical tree of adders belonging to the matrix multiplication hardware unit and a final result of the hierarchical tree of adders or any of a plurality of intermediate results of the hierarchical tree of adders is selectively provided for use in determining an output result matrix.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 6, 2022
    Assignee: Meta Platforms, Inc.
    Inventors: Yuchen Hao, Krishnakumar Narayanan Nair, Ehsan Khish Ardestani Zadeh, Rakesh Komuravelli, Abdulkadir Utku Diril, Thomas Mark Ulrich
  • Patent number: 11513890
    Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command form a host device, collect environment data of the memory device, decode data associated with the read command, determine a bit error rate (BER) of the decoded data, compare the BER to a threshold, and determine whether the data associated with the read command is to be relocated. The environment data includes temperature, number of program/erase cycles, amount of grown defects, number of past relocations and time since last data relocation. The controller is further configured to dynamically adjust the threshold based on the collected environment data and an amount of time that has passed since a last relocation of the read command data.
    Type: Grant
    Filed: May 27, 2021
    Date of Patent: November 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Evgeny Mekhanik, Dudy David Avraham, Alexander Bazarsky
  • Patent number: 11513892
    Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 29, 2022
    Assignee: Arteris, Inc.
    Inventor: Parimal Gaikwad
  • Patent number: 11507454
    Abstract: Techniques are described for identifying patterns of memory cells in a memory array that are predictive of non-correctable errors (“corruption patterns”). The techniques described herein identify patterns of cell errors that are likely to generate errors that cannot be corrected by an error correction code (ECC). The identification of non-correctable cells is accomplished by identifying a pattern of cell errors storing bit values that deviate from corresponding expected values. The pattern of these memory cells and various combinations of the cells in the pattern are compared to patterns of cells that are known to be correctable using ECC. If the error pattern or one or more of the combinations of erroneous cells in the pattern are not associated with patterns that are correctable via ECC, the error pattern is identified as predictive of a likely uncorrectable error.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: November 22, 2022
    Assignee: Oracle International Corporation
    Inventor: Benjamin John Fuller
  • Patent number: 11509346
    Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: November 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho, William Wu Shen
  • Patent number: 11500719
    Abstract: To improve the reliability of a memory system, data and error correction codes associated with the data can be stored in a first memory. Parity bits calculated over data bits in the first memory can be stored in a second memory. The parity bits in the second memory can be used to recover errors that are uncorrectable by the error correction codes. The first memory can be implemented, for example, using an emerging memory technology, while the second memory can be implement using a different memory technology.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: November 15, 2022
    Assignee: Amazon Technologies, Inc.
    Inventors: Charan Srinivasan, Nafea Bshara
  • Patent number: 11500720
    Abstract: A memory system includes a memory device including a plurality of memory units capable of inputting or outputting data individually, and a controller coupled with the plurality of memory units via a plurality of data paths. The controller is configured to perform a correlation operation on two or more read requests among a plurality of read requests input from an external device, so that the plurality of memory units output plural pieces of data corresponding to the plurality of read requests via the plurality of data paths based on an interleaving manner. The controller is configured to determine whether to load map data associated with the plurality of read requests before a count of the plurality of read requests reaches a threshold, to divide the plurality of read request into two groups based on whether to load the map data, and to perform the correlation operation per group.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: November 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Jeen Park