Abstract: Provided are a solid state drive processing method, system, device, and a non-transitory readable storage medium. The method includes: determining a target data page that is being processed when a target solid-state drive is abnormally powered down; using a next data page of the target data page as a current data page; deciding whether a read-write error exists in the current data page; in response to deciding that a read-write error exists in the current data page, using a next data page of the current data page as the current data page, and returning to execute the deciding whether a read-write error exists in the current data page; and in response to deciding that no read-write error exists in the current data page, storing target data since the next data page of the current data page.

Abstract: A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

Abstract: A read voltage calibration method, a memory storage device, and a memory control circuit unit are provided. The read voltage calibration method includes: reading data from a first physical unit by using multiple read voltage levels; decoding the data to obtain multiple error evaluation parameters; determining a first vector distance parameter according to a first error evaluation parameter; determining multiple candidate read voltage levels according to the first vector distance parameter and a first read voltage level; determining a target read voltage level according to one of the candidate read voltage levels; and reading the data again from the first physical unit by using the target read voltage level.

Abstract: A terminal according to one aspect of the present disclosure includes: a receiving section that receives information related to a channel state information reference signal (CSI-RS) of a terminal according to an old release; and a control section that performs control of applying rate match or puncture to a specific channel or signal regarding a resource of the CSI-RS of the terminal according to the old release. According to one aspect of the present disclosure, even when there are terminals according to different releases, each of the terminals can appropriately perform communication.

Abstract: Example channel circuits, data storage devices, and methods for using an adjustable code rate based on an extendable parity code matrix are described. Data units may be read from a storage medium. Multiple sets of parity bits may be available for different data units, different sets of parity bits having a different number of parity bits corresponding to different parity matrices and desired code rates. A primary parity matrix may provide a base code rate and one or more extended parity matrices may provide increased code rates based on additional rows for increased decoding. Error correction code (ECC) decoding may be selectively performed based on the different sets of parity bits and corresponding parity matrices, resulting in the output of a decoded data units based on the data units from the read signal.

Abstract: Methods, systems, and devices for spare substitution in a memory system are described. A controller may, as part of a background operation, assign a spare bit to replace a bit of a code word and save an indication of the spare bit assignment in a memory array. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) within a memory medium that retains the code word. An MSR corresponding to the bit to be replaced may include a quantity of erroneous bits relative to a threshold. The controller may, during a read operation, identify the spare bit in a first portion of the code word, determine the bit to be replaced based on accessing the memory array, and replace the bit with the spare bit concurrently with receiving a second portion of the code word.

Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.

Abstract: A method includes: receiving a message, via a communication link, including sensor data in a data stream from a sensor device and first reference data based on a deterministic function and a seed value; extracting the first reference data from the message; generating second reference data based on the deterministic function and the seed value; calculating a first quantity of bit errors in the first reference data based on the second reference data; calculating a bit error rate of the communication link based on the first quantity of bit errors; in response to the bit error rate exceeding a bit error rate threshold for the data stream, generating a second message representing a fault; and transmitting the second message to a second device.

Abstract: Multiple allocation units are selected from a set of solid state storage devices for storage of data. An erasure code and intra-device recovery data associated with the data are generated. The intra-device recovery data is written in each of the plurality of allocation units of the set of solid-state storage devices. The erasure code is written in a subset of the plurality of allocation units.

Abstract: A processing-in-memory (PIM) device includes an ECC logic circuit configured to generate write data and write parity from write input data when a write operation in an operation mode is performed, and generate converted data from read data and read parity when a read operation in an operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data to generate MAC operation result data.

Abstract: A method includes generating parity data corresponding to a plurality of word lines coupled to blocks of a memory device and generating additional parity data for a block based on a physical location of the block. The method can further include performing a data recovery operation based on the parity data, the additional parity data, or a combination thereof.

Abstract: A method includes obtaining input encoded data slices from memory of the storage network, where the input encoded data slices include a set of encoded data slices interspersed with a set of auxiliary data slices, where a data segment was error encoded into the set of encoded data slices, and where auxiliary data was error encoded into the set of auxiliary data slices. The method further includes obtaining de-selection information associated with the input encoded data slices and de-selecting the sequence of input encoded data slices based on the de-selection information to produce deselected encoded data slices. The method further includes error decoding at least a decode threshold number of encoded data slices of the deselected encoded data slices in accordance with error decoding parameters to reproduce the data segment. The method further includes outputting the data segment to a requesting computing device of the storage network.

Abstract: A memory controller is provided that is configured to control a memory accessed by a device connected to a host processor via a bus. The memory controller is configured to control a memory accessed by a device connected to a host processor via a bus, and includes a first interface circuit configured to communicate with the host processor; a second interface circuit configured to communicate with the memory; an error detection circuit configured to detect an error present in data received from the second interface circuit in response to a first read request received from the first interface circuit; a variable error correction circuit configured to correct the error based on at least one of a reference latency and a reference error correction level included in a first error correction option; and a fixed error correction circuit configured to correct the error in parallel with an operation of the variable error correction circuit.

Abstract: Various example embodiments provide efficient jitter control by means of a hybrid automatic repeat request (HARQ) process. Abase station may transmit to a UE a forwarding time parameter for data packet(s) associated with a HARQ process. The UE 110 may store the data packet(s) in a HARQ buffer and determine to hold the data packet(s) in the HARQ buffer until a delivery time determined based on the forwarding time parameter. Once the delivery time has been reached, the UE may forward the data packets to higher protocol layers. This enables efficient jitter control of a data packet flow. Apparatuses, methods, and computer programs are disclosed.

Abstract: A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

Abstract: Methods, systems, and devices for memory operations are described. A read command may be received at a memory device from a host device. As part of an error control operation, a first set of error control bits may be generated for the set of data. Based on the first set of error control bits, a failure of a matching operation associated with the error control operation may be determined. Based on determining the failure of the matching operation, a second set of error control bits that is different than the first set of error control bits may be transmitted to the host device. The second set of error control bits may indicate that the matching operation failed at the memory device.

Abstract: A semiconductor memory device includes a memory cell array, a link error correction code (ECC) engine and on-die ECC engine. The memory cell array includes a plurality of volatile memory cells. The link ECC engine provides a main data by performing a first ECC decoding on a first codeword including the main data and a first parity data, and generates a first error flag based on a result of the first ECC decoding. The on-die ECC engine generates a second parity data by performing a first ECC encoding on the main data, provides a target page of the memory cell array with a second codeword including the main data and the second parity data in response to the first error flag being deactivated or generates a third codeword by changing at least one of bits of the second codeword in response to the first error flag being deactivated.

Abstract: Methods, systems, and apparatuses for a memory device (e.g., DRAM) including an error check and scrub (ECS) procedure in conjunction with refresh operations are described. The ECS procedure may include read/modify-write cycles when errors are detected in code words. In some embodiments, the memory device may complete the ECS procedure over multiple refresh commands, namely by performing a read (or read/modify) portion of the ECS procedure while a first refresh command is executed, and by performing a write portion of the ECS procedure while a second refresh command is executed. The ECS procedure described herein may facilitate avoiding signaling conflicts or interferences that may occur between the ECS procedure and other memory operations.

Abstract: A data storage system employing distributed memories can have at least one host connected to a plurality of data storage devices via a network controller. One or more performance bottlenecks through the network controller may be identified with a performance module. A peer group consisting of at least two of the plurality of data storage devices is created with the performance module in response to the identified performance bottleneck so that a task can be assigned by the performance module to the peer group. The task may be chosen to mitigate the performance bottleneck by avoiding involvement of the network controller in the task.

Abstract: A Solid State Drive (SSD) is disclosed. The SSD may include an interface to receive read and write requests from an application on a host. Storage, including at least one chip, may store data. An SSD controller may process the read and write requests from the application. A configuration module may configure the SSD. Storage may include a reliability table which may include entries specifying configurations of the SSD and reliabilities for those configurations.