Abstract: A method of testing an integrated circuit device includes detecting a number of integrated clock gates (ICGs) in the device. Each ICG can stop clock propagation in a respective branch of a clock tree of the device. For each detected ICG, an ICG fanout (a number of digital inputs that the output of each ICG can feed) is compared with a threshold number of registers. When the ICG fanout is greater than the threshold number, it is determined whether a function-enable path of an existing ICG is timing-critical. When the function-enable path of the existing ICG is timing-critical, an additional ICG and a test point are inserted into the device as a clock input to the existing ICG. When the function-enable path of the existing ICG is not timing-critical, a test point and an AND-gate may be inserted in that function-enable path.

Abstract: Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.

Abstract: A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

Abstract: A memory device, such as a MRAM device, includes a plurality of memory macros, where each includes an array of memory cells and a first ECC circuit configured to detect data errors in the respective memory macro. A second ECC circuit that is remote from the plurality of memory macros is communicatively coupled to each of the plurality of memory macros. The second ECC circuit is configured to receive the detected data errors from the first ECC circuits of the plurality of memory macros and correct the data errors.

Abstract: Systems and techniques that facilitate Stark shift cancellation are provided. In various embodiments, a system can comprise a control qubit that is coupled to a target qubit. In various cases, the control qubit can be driven by a first tone that entangles the control qubit with the target qubit. In various aspects, the control qubit can be further driven by a second tone simultaneously with the first tone. In various cases, the second tone can have an opposite detuning sign than the first tone. In various instances, the first tone can cause a Stark shift in an operational frequency of the control qubit, and the second tone can cancel the Stark shift.

Abstract: After data to be written to a storage device, such as a solid state drive (SSD), is received from a host system, the received data is encoded using a first error correction code to generate first parity data. A temperature at which memory cells of the storage device will store the received data is determined. In response, a first portion of the received data is identified (e.g., data in memory storage that is error-prone at a predicted higher temperature that has been determined based on output from an artificial neural network using sensor(s) input). The first portion is encoded using a second error correction code to generate second parity data. The second error correction code has a higher error correction capability than the first error correction code. The encoded first portion, the first parity data, and the second parity data are stored in the memory cells.

Abstract: Various embodiments provide block failure protection for a memory sub-system that supports zones, such a memory sub-system that uses a RAIN (redundant array of independent NAND-type flash memory devices) technique for data error-correction. For some embodiments, non-parity zones of a memory sub-system that are filling up at a similar rate are matched together, a parity is generated for stored data from across the matching zones, and the generated parity is stored in a parity zone of the memory device.

Abstract: A method for compressing a signal, the method comprising: acquiring, via a signal recording module, a primary signal; modelling, via a processor, a model signal of the primary signal by: acquiring, via the processor, a sampled signal; acquiring, via the processor, a windowed signal; and extracting, via the processor: a fundamental frequency waveform having a fundamental magnitude and a fundamental phase; and at least one harmonic frequency waveform having a harmonic magnitude and a harmonic phase; wherein the model signal comprises the fundamental frequency waveform and the at least one harmonic frequency waveform; calculating, via the processor, an error signal between a reconstructed signal and the primary signal; determining, via the processor, an optimal gain from at least; an averaging step providing an average value, a predefined threshold, and a scaled signal.

Abstract: The disclosure describes a syndrome decoder circuit including: a syndrome computation circuit configured to receive K bits of message bits and P bits of parity bits to calculate S bits of syndrome bits; a X bits weight correction circuit configured to receive multiple sets of first number of bits of the syndrome bits and a first digits of the K bits of message bits to generate a first set of correction masks for the first digits of K bits of message bits; and a X?1 bits weight correction circuit configured to receive multiple sets of second number of bits of the syndrome bits and a second digits of the K bits of message bits to generate a second set of correction masks for the second digits of K bits of message bits. The first number is not equal to the second number.

Abstract: According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K, a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Abstract: A processing-in-memory (PIM) device includes a data register configured to store reference value data, and a multiplication/accumulation (MAC) operator configured to perform a comparison operation, a multiplication operation, and an addition operation on first data and second data, based on the reference value data to generate MAC operation result data when a MAC operation is performed.

Abstract: A method may comprise receiving a first signal comprising first LDPC bits including systematic bits and parity bits and transmitting information indicating that the first signal was incorrectly received. A second signal comprising second LDPC bits may be received in response to the transmitting. The second signal may include LDPC bits according to a lifting size of an LDPC base graph.

Abstract: A storage device includes a non-volatile memory device that includes memory blocks each including one or more memory cells, a combo integrated circuit (IC) that includes a temperature sensor and a memory, and a controller that is connected with the combo IC through first channels and controls the non-volatile memory device to write or read data in or from selected memory cells. When the controller determines that a first event occurs based on temperature data read from the combo IC, the controller records first event data in the memory of the combo IC. In a first operation mode, the combo IC outputs the first event data to the controller through the first channels. In a second operation mode, under control of an external host, the combo IC outputs the first event data to the external host through second channels different from the first channels.

Abstract: Data storage circuitry has entries to store data according to a data storage technology supporting non-destructive reads, each entry associated with an error checking code (ECC) and age indication. Scrubbing circuitry performs a patrol scrubbing cycle to visit each entry of the data storage circuitry within a scrubbing period. On a given visit to a given entry, the scrubbing operation comprises determining, based on the age indication associated with the given entry, whether a check-not-required period has elapsed for the given entry, and if so performing an error check on the data of the given entry using the ECC for that entry. The error check is omitted if the check-not-required period has not yet elapsed. The check-not-required period is restarted for a write target entry in response to a request causing an update to the data and the error checking code of the write target entry.

Abstract: A computing system is operable to generate a first plurality of lines of coding blocks that includes a first plurality of data blocks and a first plurality of parity blocks. A first set of segments of a first segment group that collectively include the first plurality of lines of coding blocks are generated, and the first set of segments of the first segment group are stored via a first plurality of computing devices of a first storage cluster of the computing system. A second plurality of lines of coding blocks that includes a second plurality of data blocks and a second plurality of parity blocks are generated. A second set of segments of a second segment group that collectively include the second plurality of lines of coding blocks are generated. The second set of segments of the second segment group are stored via a second plurality of computing devices of a second storage cluster of the computing system.

Abstract: An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.

Abstract: An integrated circuit device includes an n-bit register comprising: a plurality of latches and at least one flip-flop, and clock gating circuitry, which includes a clock signal coupled to the latches and the flip-flop. Each latch comprises a latch gating terminal configured to receive a gating signal, wherein a respective latch is configured to receive the gating signal that either corresponds to the clock signal or is determined according to a logical operation including the clock signal such that a transparency for each respective latch is controlled in dependence upon a level of the gating signal. The integrated circuit device is configured to operate in a scan test mode, wherein during a scan shift operation, an input signal terminal of the flip-flop is configured to receive a test input signal and the flip-flop is configured to load the test input signal to an output signal terminal of the flip-flop.

Abstract: A processing-in-memory (PIM) device includes an CRC logic circuit configured to generate write data and a write fail check signal from write input data when a write operation in an operation mode is performed, and generate a fail flag signal and converted data from read data and a read fail check signal when a read operation in the operation mode is performed; and a MAC operator configured to perform a MAC arithmetic operation for the converted data and buffer data, based on the fail flag signal to generate MAC operation result data.

Abstract: A solution is proposed for error processing, wherein n byte error positions of n byte errors are predefined (where n is a positive integer), wherein this involves determining whether there is a further byte error position on the basis of the n byte error positions and on the basis of n+1 error syndrome components of a first error code.

Abstract: An address and command port interface selectively enables JTAG TAP domain operations and Trace domain operations within an IC. The port carries TMS and TDI input and TDO output on a single pin and receives a clock signal on a separate pin. The addressable two pin interface loads and updates instructions and data to the TAP domain within the IC. The instruction or data update operations in multiple ICs occur simultaneously. A process transmits data from an addressed target device to a controller using data frames, each data frame comprising a header bit and data bits. The logic level of the header bit is used to start, continue, and stop the data transmission to the controller. A data and clock signal interface between a controller and multiple target devices provides for each target device to be individually addressed and commanded to perform a JTAG or Trace operation.