Patents Examined by Guy J. Lamarre
  • Patent number: 11119855
    Abstract: A computer-implemented method, according to one embodiment, is for selectively storing parity data in different types of memory which include a higher performance memory and a lower performance memory. The computer-implemented method includes: receiving a write request, and determining whether the write request includes parity data. In response to determining that the write request includes parity data, a determination is made as to whether a write heat of the parity data is in a predetermined range. In response to determining that that write heat of the parity data is in the predetermined range, another determination is made as to whether the parity data has been read since a last time the parity data was updated. Furthermore, in response to determining that the parity data has been read since a last time the parity data was updated, the parity data is stored in the higher performance memory.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Nikolas Ioannou, Timothy Fisher, Roman Alexander Pletka, Nikolaos Papandreou, Radu Ioan Stoica, Sasa Tomic, Aaron Daniel Fry
  • Patent number: 11108415
    Abstract: The invention discloses a method and a receiving device of the Viterbi algorithm. The method is applicable for a Viterbi decoder that receives an output signal generated by a convolution code encoder processing an original signal. The convolution code encoder includes M registers and M is a positive integer greater than or equal to 2. The method includes the following steps. First, for the first to the Mth data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known M initial values of the M registers. Then, for the Mth-last to the last data of the output signal, the Viterbi decoder performs the add-compare-select operation based on the known last M bits values of the original signal, thereby reducing the computational complexity of the add-compare-select unit.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 31, 2021
    Assignee: ALi Corporation
    Inventor: Lin Li
  • Patent number: 11099745
    Abstract: A memory controller having improved wear-leveling performance controls a memory device including a plurality of memory blocks. The memory controller includes a read operation controller, a cell state determiner, and a read reclaim controller. The read operation controller controls the memory device to read selected memory cells of a first block among the plurality of memory blocks by using at least one reference voltage. The cell state determiner compares a number of memory cells among the selected memory cells that are read as first memory cell with a reference number corresponding to the at least one reference voltage, and generates cell state information indicating a memory cell degradation degree corresponding to at least one state. The read claim controller controls the memory device to copy data stored in the first block to a second block, based on a comparison between the memory cell degradation degree with a threshold degradation degree.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: August 24, 2021
    Assignee: SK hynix Inc.
    Inventors: Seon Ju Lee, Min Hwan Moon
  • Patent number: 11101821
    Abstract: A method for polar encoding includes: receiving a message including information bits; encoding the message using a first polar code to obtain a first codeword; and encoding the message using a second polar code to obtain a second codeword. The second codeword includes two parts, and the first part of the second codeword is same as the first codeword. The method for polar encoding also includes transmitting the first codeword to a receiver in a first transmission; and transmitting the second part of the second codeword in a second transmission without transmitting the first part of the second codeword when the receiver is unable to decode the message based on the first codeword.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 24, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Gongzheng Zhang, Huazi Zhang, Chen Xu, Rong Li, Jun Wang, Lingchen Huang
  • Patent number: 11101822
    Abstract: A data writing method, a memory control circuit unit and a memory storage apparatus are provided. The method includes: receiving first data and second data from a host system; generating a first array error correcting code based on the first data, and generating a second array error correcting code based on the second data; programming a first group including the first array error correcting code into a first chip enable group by using a first programming mode; and programming a second group including the second array error correcting code into a second chip enable group by using a second programming mode.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: August 24, 2021
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Ping-Cheng Chen
  • Patent number: 11099931
    Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: August 24, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Kengo Kurose, Masanobu Shirakawa
  • Patent number: 11095333
    Abstract: A transceiver disposed on a first die in a bidirectional differential die-to-die communication system is disclosed. The transceiver includes a transmission section configured to modulate a first data onto a carrier signal having a first frequency for transmission via a bidirectional differential transmission line; and a reception section configured to receive signals from the bidirectional differential transmission line, the reception section including a filter configured to pass frequencies within a first passband that includes a second frequency, the first frequency being outside of the first passband. According to some embodiments, the reception section is configured to receive, via the bidirectional differential transmission line, modulated data at the second frequency at a same time that the transmission section transmits the modulated data at the first frequency.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: August 17, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Huan-Neng Chen, Chewn-Pu Jou, Feng-Wei Kuo, Lan-Chou Cho, William Wu Shen
  • Patent number: 11095309
    Abstract: Provided is an optical transmission/reception device including an error correction decoding unit (36) for decoding a received sequence encoded with an LDPC code, in which the error correction decoding unit (36) is configured to perform decoding processing using a parity check matrix (70) of a spatially-coupled LDPC code, which includes a plurality of parity check sub-matrices (71) combined with each other, in which the decoding processing is windowed decoding processing that uses a window (80) over one or more parity check sub-matrices (71), and in which a window size of the window (80) and a decoding iteration count due to throughput and requested correction performance are variable and input from a control circuit (12) connected to the error correction decoding device (36).
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: August 17, 2021
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kenji Ishii, Kazuo Kubo, Kenya Sugihara, Hideo Yoshida
  • Patent number: 11095307
    Abstract: Apparatuses, systems, and techniques to compute cyclic redundancy checks use a graphics processing unit (GPU) to compute cyclic redundancy checks. For example, in at least one embodiment, an input data sequence is distributed among GPU threads for parallel calculation of an overall CRC value for the input data sequence according to various novel techniques described herein.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: August 17, 2021
    Assignee: NVIDIA Corporation
    Inventor: Andrea Miele
  • Patent number: 11093173
    Abstract: According to one embodiment, in a memory system, a memory controller is configured to execute a first operation of observing an optimum value of a read voltage and updating a set value based on the observation result of the optimum value, at a predetermined time point of a plurality of time points for updating the set value of the read voltage for a plurality of memory cells, and execute a second operation of updating the set value based on the set value updated at one previous time point without executing the observation of the optimum value, at a time point after one time point of the predetermined time point.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 17, 2021
    Assignee: Kioxia Corporation
    Inventors: Ryo Yamaki, Gibeom Park, Youyang Ng, Koji Horisaki, Kazuhisa Horiuchi
  • Patent number: 11079962
    Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: August 3, 2021
    Assignee: Pure Storage, Inc.
    Inventors: John Davis, John Hayes, Brian Gold, Shantanu Gupta, Zhangxi Tan
  • Patent number: 11061768
    Abstract: A black box device for a vehicle includes a data storage system for recording event data fed to the black box from various vehicle sensors. The data storage system includes a memory having memory cells and a controller in communication with the memory. The controller is configured to receive data and determine one or more memory cells as a destination for the data to be written. The controller is configured to determine a wear level of the memory cells and select a subset of program states of the memory cells based on the wear level; and program the memory cells using respective subsets of program states for each respective memory cell.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: July 13, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Idan Alrod, Judah Gamliel Hahn, Ariel Navon, Eran Sharon, Dudy Avraham
  • Patent number: 11061772
    Abstract: According to one general aspect, an apparatus may include a host interface circuit configured to receive offloading instructions from a host processing device, wherein the offloading instructions instruct the apparatus to compute an error correction code associated with a plurality of data elements. The apparatus may include a memory interface circuit configured to receive the plurality of data elements. The apparatus may include a plurality of memory buffer circuits configured to temporarily store the plurality of data elements. The apparatus may include a plurality of error code computation circuits configured to, at least in part, compute the error correction code without additional processing by the host processing device.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: July 13, 2021
    Inventors: Mian Qin, Joo Hwan Lee, Rekha Pitchumani, Yang Seok Ki
  • Patent number: 11057163
    Abstract: In certain embodiments, a method includes repeatedly transmitting, by a first device, first data to a second device within a first time unit set. The first data is determined based on a first redundancy version and to-be-transmitted system bits. The first time unit set includes K time units, K?3, and K is an integer. The method further includes when a first condition is met, stopping, by the first device, transmitting the first data in the Mth time unit, where 2?M?K, and M is an integer.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Juan Zheng, Lei Guan
  • Patent number: 11057053
    Abstract: Systems and methods of communicating using asymmetric polar codes are provided which overcome the codeword length constraints of systems and methods of communicating that use traditional polar codes. Used herein, asymmetric polar codes refers to a polarizing linear block code of any arbitrary length that is constructed by connecting together constituent polar codes of unequal length. Asymmetric polar codes may be known by other names. In comparison to conventional solutions for variable codeword length, asymmetric polar codes may provide more flexibility, improved performance, and/or reduced complexity of decoding, encoding, or code design. The system and method provide a flexible, universal, and well-defined coding scheme and to provide sound bit-error correction performance and low decoding latency (compared with current length-compatible methods which can be used with current hardware designs).
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 6, 2021
    Assignees: Huawei Technologies Co., Ltd., The Royal Institution for the Advancement of Learning/McGill University
    Inventors: Warren Jeffrey Gross, Adam Christian Cavatassi, Thibaud Tonnellier, Yiqun Ge
  • Patent number: 11036581
    Abstract: An apparatus includes a non-volatile storage circuit that includes a primary copy of a data value in a first storage location and a redundant copy of the data value in a second, different storage location. The data value includes one or more bits. The apparatus further includes an error detection circuit configured to retrieve contents of the first and second storage locations in response to a request for the data value. The error detection circuit is further configured to perform an error correction operation on the retrieved contents of the first and second storage locations to generate a data output responsive to the request, and to perform an error detection operation to generate an error signal that indicates whether the retrieved contents of the first and second storage locations are different.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Apple Inc.
    Inventors: Wei Chen, Sanjay Pant
  • Patent number: 11036579
    Abstract: Decoder is provided for memory systems. The decoder receives data from a memory device including a plurality of pages, each storing data, and decoding the data based on a type of a page in which the data is stored, among the plurality of pages and life cycle information indicating a current state of the memory device in its life cycle.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventors: Chenrong Xiong, Aman Bhatia, Fan Zhang, Naveen Kumar, Xuanxuan Lu, Yu Cai
  • Patent number: 11037650
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Patent number: 11036582
    Abstract: An apparatus comprising non-volatile memory is configured to access a selected unit of encoded SLC data in the non-volatile memory during a first programming phase of a process of folding data stored at a single bit per memory cell to data stored at multiple bits per memory cell. The apparatus recovers the selected unit of SLC data based on redundancy data formed from units of SLC data that data include the selected unit of SLC data. The apparatus saves the recovered selected unit of SLC data to memory. The apparatus uses the saved recovered unit of SLC data during a second programming phase of folding the data stored at a single bit per memory cell to the data stored at multiple bits per memory cell, thereby saving considerable time in not having to again recover the SLC data using the redundancy data.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: June 15, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Raghavendra Gopalakrishnan, Bhanushankar Doni, Manohar Srinivasaiah
  • Patent number: 11031953
    Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARQ) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: June 8, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Joseph Richardson, Shrinivas Kudekar