Abstract: A memory system includes a nonvolatile memory which comprises a plurality of memory cells capable of storing 4-bit data represented by first to fourth bits by sixteen threshold regions, and a memory controller configured to cause the nonvolatile memory to execute a first program for writing data of the first bit, the second bit, and the fourth bit and then causes the nonvolatile memory to execute a second program for writing data of the third bit. In fifteen boundaries existing between adjacent threshold regions among the first to sixteenth threshold regions, a maximum value of the number of first boundaries used for determining a value of the data of the first bit, the number of second boundaries used for determining a value of the data of the second bit, the number of third boundaries used for determining a value of the data of the third bit.

Abstract: A memory device includes a data array, a parity array and an ECC circuit. The ECC circuit is coupled to the data array and the parity array. In a first test mode, the ECC function of the ECC circuit is disabled, and in a second test mode, the ECC circuit directly accesses the parity array to read or write parity information through the parity array.

Abstract: Some memory dice in a stack can be connected externally to the stack and other memory dice in the stack can be connected internally to the stack. The memory dice that are connected externally can act as interface dice for other memory dice that are connected internally thereto. Data protection and recovery schemes provided for the stacks of memory dice can be based on data that are transferred in a single data stream without a discontinuity between those data transfers from the memory dice of the stacks.

Abstract: A quasi-volatile memory (QV memory) stack includes at least one semiconductor die, having formed thereon QV memory circuits, bonded to a second semiconductor on which a memory controller for the QV memory (“QV memory controller”) is formed. The circuits in the bonded semiconductor dies are electrically connected using numerous copper interconnect conductors and conductive through-silicon vias (TSVs). The QV memory controller may include one or more interfaces to additional devices (“back-channel devices”) to enable the QV memory controller to also serve as a controller for each back-channel device and to provide additional services. The QV memory controller performs data transfers between a back-channel device and the QV memory without intervention by the host CPU.

Abstract: The embodiments herein provide a system and method for generating a catalog of graphs that acts as a source for creating error correcting codes. A D3 chord index notation is used to describe the graphs. A list of (3, g) Hamiltonian graphs for even girth g is created to satisfy the condition 6?g?16. Each of the lists is infinite and is used for creating LDPC codes of high quality.

Abstract: Techniques for device modification analysis are disclosed. For example, a method comprises collecting operational data from one or more devices, and receiving one or more modifications to at least one of firmware and software for the one or more devices. In the method, one or more virtual instances of respective ones of the one or more devices are generated, and the one or more modifications are tested on the one or more virtual instances to determine if there are one or more issues with the one or more modifications.

Abstract: Systems and methods that enable hardware memory error tolerant software systems. For instance, the system may comprise a host device that instantiates a kernel agent in response to one or more requests to access hardware memory, determines, by the kernel agent based on the received information, whether the request to access memory will cause access to a corrupt memory location, and skip an operation associated with the corrupt memory location in response to determining that the request will access a corrupt memory location. The systems may also include a system that detects software vulnerabilities to hardware memory errors.

Abstract: A method in a sending node of a communications network includes: encoding a transport block, TB, including data of at least one protocol data unit, PDU, to generate a code block group, CBG, comprising one or more code blocks; defining a CBG header indicative of a starting location of a first PDU within the CBG; and transmitting the CBG including the CBG header. A method in a receiving node includes: receiving one or more code block groups, CBGs, each CBG comprising a CBG header indicative of a start location of a first protocol data unit, PDU, within the CBG; attempting to decode each received CBG; responsive to failing to decode a first CBG, attempting to decode a second CBG, and responsive to successfully decoding the second CBG: identifying the start location of the first PDU in the second CBG; buffering data of the second CBG prior to the identified start location; and forwarding data of PDUs following the identified start location.

Abstract: According to one general aspect, an apparatus may include a regeneration-code-aware (RCA) storage device configured to calculate at least one type of data regeneration code for data error correction. The RCA storage device may include a memory configured to store data in chunks which, in turn, comprise data blocks. The RCA storage device may include a processor configured to compute, when requested by an external host device, a data regeneration code based upon a selected number of data blocks. The RCA storage device may include an external interface configured to transmit the data regeneration code to the external host device.

Abstract: Systems and methods herein provide for error correction via Low Density Parity Check (LDPC) coding. In one embodiment, a system includes a data buffer operable to receive a block of Low Density Parity Check (LDPC) encoded data. The system also includes a processor operable to reduce a belief propagation algorithm used to encode the LDPC encoded data into a quadratic polynomial, to embed the quadratic polynomial onto a plurality of quantum bits (qubits), and to decode the block of LDPC encoded data via the qubits.

Abstract: A soft-decision decoding computes a first syndrome polynomial in accordance with a received word, computes a second syndrome polynomial by multiplying the first syndrome polynomial by a locator polynomial based on locations of erasures within the received word, finds a basis and private solution to an affine space of polynomials that solve key equations based on the second syndrome polynomial, determines a weak set of a locations of symbols in the received word with confidence below a certain confidence level, computes a matrix from the basis, the private solution and the weak set, determines sub-matrices in the matrix whose rank is equal to a rank of the matrix, determines error locator polynomial (ELP) candidates from the sub-matrices, the basis, and the private solution, and corrects the received word using a selected one of the ELP candidates.

Abstract: A method for indicating a sidelink HARQ feedback includes: allocating a target resource to a user equipment to perform sidelink communication; sending a downlink control signaling to the user equipment, where the downlink control signaling includes the target resource and first indication information; the first indication information indicates at least one of the followings: when the user equipment uses the target resource allocated by the base station to perform sidelink unicast communication, whether to perform the sidelink HARQ feedback; when the user equipment uses the target resource allocated by the base station to perform sidelink multicast communication, whether to perform the sidelink HARQ feedback; when the user equipment uses the target resource allocated by the base station to perform the sidelink multicast communication, a feedback manner of performing the sidelink HARQ feedback.

Abstract: Error correction code (ECC) coding for key-value data storage devices. In one embodiment, a controller includes a memory interface configured to interface with a memory; an ECC engine configured to perform ECC coding on data stored in memory; a controller memory including a flash translation layer and a namespace database; and an electronic processor. The electronic processor is configured to receive data to be stored, separate the data into a plurality of sub-code blocks, and allocate parity bits to each sub-code block of the plurality of sub-code blocks.

Abstract: A high-dimensional non-orthogonal transmission method is provided. In the method, signals of various users are mapped to form high-dimensional signals, and the high-dimensional signals are pre-coded, such that non-orthogonal transmission is realized in a higher dimension. Moreover, different users perform matched receiving on respective signals, and non-orthogonal transmission signals can be recovered merely by means of a receiver with a linear complexity. By means of the method, multi-user data non-orthogonal transmission can be realized without depending on conditions such as user pairing and collaboration, and various users do not need to perform iterative feedback, such that the detection complexity of non-orthogonal multi-user signals is significantly reduced.

Abstract: Techniques are disclosed relating to memory error tracking and logging. In some embodiments, a memory cache controller circuitry is configured to track, using multiple circuit entries, numbers of detected correctable errors associated with multiple respective locations, and in response to detecting a threshold number of correctable errors for a particular location, generate a signal to the one or more processors that identifies the particular location. In some embodiments, the memory cache controller circuitry includes multiple circuit entries for tracking uncorrectable errors.

Abstract: A method for operating a memory includes: reading data and an error correction code from a memory core; correcting an error of the read data based on the read error correction code to produce error-corrected data; generating new data by replacing a portion of the error-corrected data with write data, the portion becoming a write data portion; generating a new error correction code based on the new data; and writing the write data portion of the new data and the new error correction code into the memory core.

Abstract: A read-disturb-based read temperature determination system includes a storage device that is coupled to a read temperature adjustment subsystem. The storage device receives data from the read temperature adjustment subsystem, stores the data in a block in the storage device, identifies read disturb information for a row in the block at a plurality of different times, processes the read disturb information to generate a read temperature for the row, provides the read temperature in a local logical storage element read temperature map and, based on instructions from the read temperature adjustment subsystem, adjusts the read temperature provided in the local logical storage element read temperature map.

Abstract: A method of operating a memory device is provided. The method includes: receiving a first command from a controller; activating a page of a memory cell array based on the first command; reading data of the activated page; detecting an error from the read data; correcting the detected error to generate error correction data; writing back the error correction data to the activated page in based on the detected error being a single-bit error; and blocking write-back of the error correction data to the activated page based on the detected error being a multi-bit error.

Abstract: A non-volatile solid-state storage is provided. The non-volatile solid state storage includes a non-volatile random access memory (NVRAM) addressable by a processor external to the non-volatile solid state storage. The NVRAM is configured to store user data and metadata relating to the user data. The non-volatile solid state storage includes a flash memory addressable by the processor. The flash memory is configured to store the user data responsive to the processor directing transfer of the user data from the NVRAM to the flash memory.

Abstract: Disclosed are various embodiments for improving the resiliency and performance of clustered memory. A computing device can generate at least one parity page from at least a first local page and a second local page. The computing device can then submit a first write request for the first local page to a first one of a plurality of memory hosts. The computing device can also submit a second write request for the second local page to a second one of the plurality of memory hosts. Additionally, the computing device can submit a third write request for the parity page to a third one of the plurality of memory hosts.