Abstract: A method authenticates nodes in a communication network of an automation installation. Respective authentication information is transmitted to an authentication server, which takes the authentication information as a basis for admitting or rejecting the nodes in the communication network as subscribers. In order to be able to perform an authentication of a node even in a communication network configured with redundancy, the communication network contains multiple nodes, each of which has at least two communication ports. The communication network executes a spanning tree protocol and at least two of the nodes use their mutually facing communication ports to interchange authentication requests and send the respective received authentication information to an authentication server, connected to the communication network, that uses the respective received authentication information to perform a check on the authenticity of the node and admits or rejects the node in the communication network based on the check.

Abstract: Systems and methods are described herein that allow information carrying bits of a transmission block to be placed at higher-reliability positions prior to transmission. An exemplary method includes generating a set of payload bits to be encoded for transmission, wherein the set of payload bits includes at least one known bit, interleaving the set of payload bits to generate an interleaved set of payload bits, wherein the interleaved set includes the at least one known bit in a predetermined position in the interleaved set, providing the interleaved set to a cyclic redundancy check (CRC) encoder to generate CRC-interleaved set of payload bits, wherein the CRC-interleaved set includes the at least one known bit in a predetermined position within the CRC-interleaved set, and encoding the CRC-interleaved set for transmission to a wireless device. Associated network nodes and wireless devices are included.

Abstract: A system using accelerated error-correcting code in the storage and retrieval of data, wherein a single-instruction-multiple-data (SIMD) processor, SIMD instructions, non-volatile storage media, and an I/O controller implement a polynomial coding system including: a data matrix including at least one vector and including rows of at least one block of original data; a check matrix including more than two rows of at least one block of check data in the main memory; and a thread that executes on a SIMD CPU core and including: a parallel multiplier that multiplies the at least one vector of the data matrix by a single factor; and a parallel linear feedback shift register (LFSR) sequencer or a parallel syndrome sequencer configured to order load operations of the original data into at least one vector register of the SIMD CPU core and respectively compute the check data or syndrome data with the parallel multiplier.

Abstract: A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

Abstract: In an embodiment, a method includes: receiving, via control lines of a parallel interface of a memory device, a first command and a first read command including one or more bits indicative of a first selection that causes a selector circuit to select data from a data memory portion of the memory device; providing, via data lines of the parallel interface, first data from the data memory portion using the selector circuit, where the provided first data is associated with the first read command; receiving, via the control lines, a second command and a second read command including one or more bits indicative of a second selection that causes the selector circuit to select data from an ECC memory portion; and providing, via the data lines, first ECC values from the ECC memory portion using the selector circuit, where the first ECC values are associated with the first data.

Abstract: An operating method of a storage device is provided. The operating method includes: receiving a host read command from a host device; identifying whether a read path corresponding to the host read command corresponds to a first direct memory access (DMA) read path; and directly outputting, by a host DMA manager, read data stored in an output buffer of an error correction circuit to the host device based on the read path corresponding to the first DMA read path.

Abstract: Methods, systems, and devices for memory operations are described. A codeword may be associated with a set of data and stored in a memory device may be detected as having a plurality of bit errors. Based on detecting the plurality of bit errors in the codeword, an address of the codeword may be stored and an indication that at least one codeword stored in the memory device has a plurality of bit errors may be indicated. Based on indicating that at least one codeword in the memory device has a plurality of bit errors, a write command for writing, to the memory device, a second codeword associated with the set of data may be received. Additionally, or alternatively, a command that triggers an error correction operation at an address range of the memory device may be received at a memory device.

Abstract: Methods, systems, and devices for error evaluation for a memory system are described. A memory device may be configured to monitor access errors of the memory device to evaluate a likelihood that such errors are related to a failure of the memory device itself or to a failure outside the memory device. For example, a memory device may monitor a respective quantity of errors for each of a set of banks and, if the memory device detects that multiple banks are associated with a threshold quantity of access errors, the memory device may infer the presence of a failure outside the memory device. The memory device may store an indication of such a detection, which may be used to support failure diagnosis or resolution efforts, such as refraining from replacing a memory device when access errors are more likely to be the result of a system failure.

Abstract: A terminal determines and reports a specific codebook-based HARQ-ACK on the basis of the result of receiving a plurality of PDSCHs, and, on the basis of a first-type codebook-based HARQ-ACK having been set for scheduling of the plurality of PDSCHs, the terminal can perform first start symbol and length indicator value (SLIV) pruning on the basis of a set of the SLIVs of PDSCHs, which can be potentially scheduled on each slot of a bundling window determined on the basis of a plurality of candidate PDSCH-to-HARQ feedback timing values, and perform second SLIV pruning on the basis of a set of the SLIVs of PDSCHs, which can be potentially scheduled even on at least one slot that does not belong to the bundling window.

Abstract: Disclosed embodiments of the present disclosure relate, generally, to systems, methods, and devices for correction of burst-errors induced during transmission of encoded blocks of information. Some embodiments relate to decoders configured to test candidate corrections on a received block of information and select a candidate correction that best fits the characteristics of burst-errors expected for a type of transmission scheme. Such tested candidate corrections may be selected based on characteristics of burst-errors typically induced for a type of transmission scheme. Some embodiments relate to decoders configured to test candidate corrections for correcting burst-errors and perform standard error correcting techniques such as Reed-Solomon forward error correction techniques. Some embodiments relate to systems, such as serial/deserializer interfaces, that incorporate such decoders.

Abstract: Systems, methods, and apparatus related to a multi-level error correction architecture used for copying data in memory devices. In one approach, user data is stored in the first partition of a non-volatile memory. First error correction code data is generated for the user data and stored with the user data in the first partition. Second error correction code data is generated for the user data and stored outside the first partition. The second error correction code data provides an increased error correcting capability that is compatible with the error correction algorithm used with the first error correction code data. A copyback operation is used to copy the user data and the first error correction code, but not the second error correction code, to a second partition of the non-volatile memory. The second error correction code can be selectively used if there is a need to recover portions of the user data stored in the first partition.

Abstract: Certain aspects of the present disclosure generally relate to techniques for puncturing of structured low-density parity-check (LDPC) codes. Certain aspects of the present disclosure generally relate to methods and apparatus for a high-performance, flexible, and compact LDPC code. Certain aspects can enable LDPC code designs to support large ranges of rates, blocklengths, and granularity, while being capable of fine incremental redundancy hybrid automatic repeat request (IR-HARD) extension while maintaining good floor performance, a high-level of parallelism to deliver high throughout performance, and a low description complexity.

Abstract: A memory device includes a first memory group including plural first non-volatile memory cells capable of storing multi-bit data, and a second memory group including plural second non-volatile memory cells capable of storing single-bit data. A program operation controller builds the multi-bit data based on data inputted from an external device, performs a logical operation regarding partial data among the multi-bit data to generate a parity, programs the parity in the second memory group after programming the partial data in the first memory group, perform a verification operation regarding the partial data after a sudden power-off (SPO) occurs, recovers the partial data based on the parity and a result of the verification operation, and programs recovered partial data in the first memory group.

Abstract: According to certain embodiments, a method by a transmitter is provided for adaptively generating precoder bits for a Polar code. The method includes acquiring at least one configuration parameter upon which a total number of precoder bits depends. The at least one configuration parameter comprising at least one of an information block length K,a code block length N, and/or a code rate R=K/N. The total number of precoder bits is determined, and the precoder bits for a code block are generated according to the determined total number of precoder bits. The precoder bits are placed within the code block.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine an error correction code (ECC) code length for KV pair data and/or an ECC code rate for the KV pair data, where the ECC code length and the ECC code rate are selected according to a value length and decoding capability of the KV pair data, generate ECC parity based on the selecting, and program the KV pair data and the generated ECC parity to the memory device.

Abstract: A storage controller includes parallel input channels configured for simultaneously receiving data from substantially redundant memories, an error estimation unit, a decision unit, an error correction unit and a selection unit. The error estimation unit generates error information by estimating an error level of the plurality of data. The decision unit performs a logical operation on the plurality of data to generate operation data. The error correction unit generates error correction data by correcting an error of the operation data. The selection unit selects one of the operation data or the error correction data based on the error information.

Abstract: According to one embodiment, provided is a storage management system having a processor and managing a plurality of storages, in which the storage has a plurality of types of components, and performs redundantization of a data to be stored by combining the plurality of components, the storage management system has component management information indicating redundancy set for the component itself, and the processor sets a method of data protection of the storage based on the component management information and a request for the data protection for the data stored in the storage.

Abstract: A memory device includes; a memory module including a memory array, and a memory controller that retrieves read data from memory cells of the memory array. The memory controller includes a fault detector that detects faulty addresses associated with faulty memory cells among the memory cells providing data errors.

Abstract: Methods, devices, and systems related to crossed matrix parity in a memory device are described. In an example, a first plurality of sets of parity data to memory cells in the array that each protect data stored in a row of memory cells of the array can be written to the array. Further, a second plurality of sets of parity data to memory cells in the array that each protect data stored in a column of memory cells of the array can be written to the array. The first plurality of sets of parity data and the second plurality of sets of parity data can be sent to a processor for further ECC processing. Error correction data can be received from a processor that indicates a cluster of data that includes a threshold quantity of errors. An error correction can be performed on the cluster of data.

Abstract: Methods, systems, and devices for a dynamic error control configuration for memory systems are described. The memory system may receive a read command and retrieve a set of data from a location of the memory system based on the read command. The memory system may perform a first type of error control operation on the set of data to determine whether the set of data includes one or more errors. If the set of data includes the one or more errors, the memory system may retrieve a second set of data from the location of the memory system and determine whether a syndrome weight satisfies a threshold. The memory system may perform a second type of error control operation on the second set of data based on determining that the syndrome weight satisfies the threshold.