Abstract: A gate driver includes a high-side region that operates in a first voltage domain, a low-side region that operations in a second voltage domain lower than the first voltage domain, a termination region interposed between the high-side region and the low-side region and configured to isolate the first voltage domain from the second voltage domain, a high-side gate driver disposed in the high-side region and configured to drive a high-side power transistor, a low-side gate driver disposed in the low-side region and configured to drive a low-side power transistor, and a plurality of termination diodes disposed in the termination region and configured to transmit information bits between the high-side region and the low-side region, where each of the plurality of termination diodes includes an anode coupled to the low-side region and a cathode coupled to the high-side region.

Abstract: A vehicle glazing with a slot antenna between the vehicle portal and the peripheral edge of an IR reflective coating that includes a heating bus over the coating edge. The antenna slot may be fed directly by a voltage probe or a coupled coplanar line at a position to excite both fundamental and higher order modes for multiband antenna applications. A portion of the IR reflective coating may overlay the window frame at null positions of first higher order mode to tune the slot antenna to higher frequencies. Slot antenna resonant frequency may also be moved higher by separating the IR reflective coating into two coating panel with the lower coating panel connected to electrical ground by capacitive coupling. Multiple antennas can be fed at different locations for multiband applications and diversity antenna systems.

Abstract: Methods, systems, and devices for leakage current reduction in electronic devices are described. Electronic devices may be susceptible to leakage currents when operating in a first mode, such as an inactive (e.g., a standby) mode. To mitigate leakage current, an electronic device may include transistors coupled in cascode configuration where a gate of a drain-side transistor in the cascode configuration is configured to be biased by an adjustable (e.g., a dynamic) control signal. When the transistors are inactive (e.g., “off”), the control signal may be adjusted to prevent leakage associated with the inactive transistors. Further, a source-side transistor in the cascode configuration may be configured to have a high threshold voltage (e.g., relative to the drain-side transistor).

Abstract: The presently disclosed invention astutely turns the potentially detrimental crosstalk effect in nanocircuitry into an advantage by engineering interference among single lines. In one embodiment, a nanocircuit logic gate within an array of nanocircuitry comprises first and second aggressor metal conductive lines; a victim line; and an inverter coupled to the victim line; wherein the first and second aggressor conductive lines are positioned to induce a signal on the victim line. In another embodiment, a nanocircuit logic gate within an array of nanocircuitry comprises first and second aggressor metal conductive lines; a control aggressor metal conductive line; a victim line; and a first inverter coupled to the victim line; wherein the first and second aggressor conductive lines and the control aggressor conductive line are positioned to induce a signal on the victim line. Further embodiments include complex computational and logic structures based on these efficient logic circuits.

Abstract: An electronic device and its antenna assembly are provided. The electronic device includes a display screen, a metal foothold, a motherboard, and an antenna assembly. The display screen and the motherboard are disposed at two opposite surfaces of the metal foothold. The antenna assembly electrically connected to the motherboard includes a metal frame, a plastic sheet, an antenna, and a conductive sheet. The metal frame is disposed at the metal foothold, and one side of the metal frame has an opening, so that the plastic sheet can be embedded in the opening. The antenna includes an antenna main board disposed at the plastic sheet and a double-sided antenna disposed at two opposite sides of the antenna main board. The conductive sheet is connected to the double-sided antenna and lapped over the metal frame.

Abstract: In an array of a plurality of plasma generator modules for generating a physical plasma by dielectric barrier discharges at atmospheric pressure, each of the plasma generator modules comprises two parallel electrodes linearly extending at a lateral distance, one of which having a dielectric barrier; connection devices for connecting the electrodes to a high voltage source; two flat gas-conducting elements conducting a working gas between the electrodes; and a module housing delimiting the respective plasma generator module laterally along the electrodes and transversely to the electrodes. The module housings are fixed to one another or to a common module frame by means of fixation devices. The module housings are arranged side by side both in a first direction along and in a second direction transverse to the electrodes, and in such an offset way that the electrodes of the plasma generator modules partially overlap in the direction along the electrodes.

Abstract: Apparatuses and methods are presented relating to a plurality of current sources for generating a plurality of first bias currents to drive a plurality of LEDs and a plurality of measurement circuits for obtaining a plurality of first voltage measurements for the LEDs during a first test cycle. The current sources are further configurable to generate a plurality of second bias currents for driving the LEDs, and the measurement circuits are further configurable to obtain a plurality of second voltage measurements for the plurality of LEDs, during a second test cycle. A memory device is configured to store the first and second bias currents and first and second voltage measurements as a current-voltage (I-V) performance characteristic.

Abstract: An apparatus includes a terminal, a first device coupled to the terminal via a first node, the first device to drive a signal on the terminal via the first node, and a second device coupled to the terminal via a second node, wherein the second device comprises a dynamic on-die termination (ODT) circuit coupled to the second node. The dynamic ODT circuit includes: a bus holder circuit to receive the signal from the first device at the second node and select a termination voltage based on the signal, a response delay circuit coupled to the bus holder circuit, the response delay circuit to delay application of the termination voltage to the second node, and a time blanking delay circuit coupled to the bus holder circuit and the response delay circuit to prevent the termination voltage from changing before a threshold period of time elapses.

Abstract: Embodiments of the present disclosure disclose a method for improving a performance of a pulsed-ultraviolet (PUV) device. The method includes monitoring an input current across a circuit breaker in communication with a UV lamp, where the input current is delivered by a power signal and is interrupted by the circuit breaker upon exceeding a predefined cut-off current; generating a pulse signal having a set of frequencies based on the power signal for driving the UV lamp, where the pulse signal is associated with a predetermined cut-off frequency that increases the input current beyond the cut-off current; determining a predefined threshold current less than the cut-off current; and configuring the pulse signal with multiple distinct pulse frequencies per second for a predefined configuration period based on the input current exceeding the threshold current. The distinct pulse frequencies per second include at least one pulse frequency greater than the cut-off frequency.

Abstract: A circuit stacking multiple asynchronous circuit components, specifically Multi-Threshold NULL Convention Logic (MTNCL) circuit components, with an overall power supply equal to the multiples of the original VDD.

Abstract: An indoor power line transmission control system, includes: a transforming dimming controller (1), which is used to load, onto an electrical signal, a received dimming signal sent by a mobile terminal or input by a user in a touch-control manner, and send the electrical signal loaded with the dimming signal to a dimming driver (2); and the dimming driver, which is electrically connected with the transforming dimming controller and a dimming luminaire (3), and used to read the electrical signal loaded with the dimming signal, and adjust a gray scale of the dimming luminaire according to the read electrical signal. By replacing a normal switch with the transforming dimming controller and by using the dimming driver and transmitting the dimming signal to the dimming luminaire by means of a power line, flexibility of having no wiring, simple extension and smart dimming are realized and energy can be saved.

Abstract: An integrated circuit including an FPGA, configurable to process data via a plurality of data processing operations, and an ASIC, electrically coupled to logic circuitry of the FPGA via switch interconnect network thereof. In one embodiment, the ASIC includes a plurality of circuit blocks, each circuit block configurable to process data via a data processing operation, and selection circuitry, coupled to the logic circuitry of the FPGA and the plurality of circuit blocks of the ASIC, configurable to connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a first circuit configuration to perform a first data processing operation, and in situ, connect one or more of the plurality of circuit blocks of the ASIC and the logic circuitry of the FPGA into a second circuit configuration to perform a second data processing operation.

Abstract: A polarization waveguide network includes a reactive transmit (TX) power splitter and multiple receive (RX)-reject waveguide filters to reject RX frequencies. The polarization waveguide network further includes a quadrature junction coupler that can couple the RX-reject waveguide filters to an antenna port. The polarization waveguide network is configured to be fabricated in three pieces with two zero-current split planes, and a first piece of the three pieces is used for coupling to the antenna port.

Abstract: In accordance with the present disclosure, one embodiment includes a memristor that is caused to be in a particular resistance state by a voltage applied across terminals of the memristor. A first logical input and a second logical input that are below a threshold voltage of the memristor are applied to a first terminal of the memristor. A first control input and a second control input are applied to a second terminal of the memristor. A logical output is determined based on a resistance state of the memristor.

Abstract: A module for a programmable controller includes a plurality of analog input channels, a control and evaluation device, and input terminals, where for each input channel, the module includes two analog to digital converters, at least four coupling elements and a switchover device, where for each input channel, where an input side of one analog to digital converter is directly or indirectly connected with the input terminals and an output side is connected with the evaluation circuit via a coupling element, where a control input of the switchover device is connected with the switching signal generator via a further coupling element, a signal output of the switchover device is connected with an input side of the other analog-to-digital converter, and where an output side of the other analog-to-digital converter is connected with the evaluation circuit via a further coupling element, where the coupling elements cause electrical isolation.

Abstract: An impedance matching method includes: calculating an output impedance of a theoretical circuit model set in advance from actual values of two variable components and a measured value of an input impedance; calculating values of the two variable components at the time of impedance matching through an arithmetic operation under a matching condition in the theoretical circuit model based on the calculated value of the output impedance assuming that the output impedance due to matching transition has the same value; and controlling the actual values of the variable components of the impedance matching device to correspond to the calculated two variable component values.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to measurement circuits for logic paths and methods of manufacture. The circuit includes: a flip flop device outputting an output signal comprising an intrinsic delay; a logic path looping the output signal back to the flip flop device such that the intrinsic delay is to be received by the flip flop device; and an oscillator which feeds an input signal into the logic path and sweeps the input signal to alter the looped output signal thereby providing a maximum frequency of the logic path.

Abstract: A quantum computing D-state AC-Stark shift gate system comprises at least one gate manipulation source and one or more ions trapped in an ion trap. The at least one gate manipulation source is configured to generate a first gate manipulation signal and a second gate manipulation signal. The first and second gate manipulation signals couple an ion between a set of S-states and a set of D-states. The first and second gate manipulation signals apply a force to an ion of the one or more ions that is dependent on the internal state of the ion. The first and second gate manipulation signals are configured to couple internal states of the ions to their motional state without appreciably altering a population of the ions within the set of S-states.

Abstract: Techniques and mechanisms for mitigating signal deterioration in communications between two circuit boards. In an embodiment, a packaged device accommodates coupling to a first circuit board which, in turn, accommodates connection to a second circuit board. In one such embodiment, an amplifier circuit of the packaged device includes an amplifier circuit which comprises a variable resistor and an active circuit element coupled thereto. The device receives via one of the circuit boards a control signal and a voltage which configure the amplifier circuit to provide an impedance matching for communication between the circuit boards. In another embodiment, the device comprises multiple common gate amplifiers which are variously configurable each to provide a respective impedance matching for communications between a motherboard and a dual in-line memory module.

Abstract: A calibration device includes a first comparator that outputs a first result of comparing a level of a first voltage of a first node and a level of a reference voltage, a second comparator that outputs a second result of comparing the level of the first voltage and a level of a second voltage of a second node, and a control signal generator that outputs a first signal for adjusting a first resistance value of a first resistor circuit based on the first result and to output a second signal for adjusting a second resistance value of a second resistor circuit based on the second result. The first node is between the first resistor circuit and a reference resistor, and the second node is between the second resistor circuit and a third resistor circuit which is adjusted to have the same resistance value as the first resistance value.