Abstract: The present invention provides methods and modules allowing for mapping of interface signals at for instance multi-line buses. A mapping of internal signal order schemes to external signal order schemes is enabled such that upon configuration any interface signals may carried on any lines of a multi-line bus. The configurability may obtained by the implementation of mapping logics and mapping algorithms, which associates external interface terminal to signal association to internal interface terminal to signal association in a configurable manner.

Abstract: The present invention provides a method for releasing data of a storage apparatus. The method manages the data output of the storage apparatus by using a virtual output queue, a data storing memory, and a bit map output port memory. In such method, the output ports, which use the data stored in any data column of the data storing memory, are recorded in the bit map output port memory. In addition, the addresses of the data storing memory for storing the data output from any output port are provided by the virtual output queue. After all data of a certain data column is completed read out, the data storing column in the data storing memory and a corresponding part of the bit map output port memory are released by the storage apparatus.

Abstract: An improved remote USB access method allows a local host to access USB devices on a remote host in a manner that reduces network traffic in certain situations. When the local host copies a file from a USB device A to a USB device B both located on the remote host, the operation is initially handled in a conventional manner by which data is transferred from device A to the local host over the network, and then from the local host to device B over the network. The remote host is provided with an ability to detect such an operation as a special case where the data transfer from the local host to device A is unnecessary. Thus, the remote host copies the data from device A to device B, and notifies the local host to stop the network data transfer from the local host to device B.

Abstract: A method for programming a touch screen of an apparatus is provided. The touch screen includes sensors for sensing locations of inputs and generating corresponding signals, and keys each of which consisting of a group of the sensors. The method includes: designing a group of the sensors as a key; setting an associated function to the designed key; generating a layout file of the designed keys; showing the layout file to prompt position and the associated function of each of the keys; acquiring the associated functions according to the key indicated by the signals; and executing the acquired functions.

Abstract: Provided is a system comprising a first node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the first node connect via their processor fabrics; a second node comprising a plurality of processor cards each including a processor fabric, wherein the processor cards in the second node connect via their processor fabrics; and a plurality of communication interfaces, wherein each interface connects one processor card in the second node to one processor card in the first node to enable communication between the connected processor cards to coordinate processor operations between the connected processor cards in the first and second nodes.

Abstract: Apparatus, methods, systems, and computer-readable media are provided for remotely controlling the connection between a host computer and a multitude of connected devices. One apparatus described herein includes a multiplexer that has a host port for connection to a host computer, device ports for connection to the devices, and control lines. The multiplexer is operative to connect a device port to the host port based upon the status of the control lines. The apparatus further includes a controller connected to the multiplexer. The controller has an input interface and is operative to receive control data on the input interface that identifies a device port on the apparatus that should be connected to the host port. In response to receiving such control data, the controller is operative to place signals on the control lines that cause the multiplexer to connect the identified device port to the host port.

Abstract: The present invention introduces the notions of a rendezvous component and rendezvous functionality into the communications network environment. Using the invention, an application can express information regarding when an operation requested of a device should complete and at which location, and it enables the device to perform its operations respecting this information while also improving the device's overall behavior. In an embodiment, one or more data objects are distributed across one or more collections of storage devices using a dispersal technique. When access to a data object is desired, a rendezvous component issues a set of constituent requests to the collections of storage devices. These requests typically include location and timing rendezvous parameters specifying a destination location where and a given time when a given data object is to be reconstituted.

Abstract: A system and method for control management of shared peripheral circuits by a plurality of controllers is provided. Control of the peripherals is mediated through a shared signal controller which uses mask registers to ensure that only one controller may control a peripheral at any one time, and that the type of peripheral is matched to the type of controller.

Abstract: The invention generally relates to a communication adapter for use with an ambulant medical device. The device carries out a data transmission to the communication adapter that carries out a data transmission to a computer by means of a data connection. The communication adapter processes the data to be read-out from the devices in such a fashion that it can be displayed on a computer without the use of specific software.

Abstract: A computer program product and distributed data processing system that allows a single physical I/O adapter, such as a PCI, PCI-X, or PCI-E adapter, to validate that a direct memory access address referenced by an incoming I/O transaction that was initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation is provided. Specifically, the present invention is directed to a mechanism for sharing conventional PCI (Peripheral Component Interconnect) I/O adapters, PCI-X I/O Adapters, PCI-Express I/O Adapters, and, in general, any I/O adapter that uses a memory mapped I/O interface for communications. A single physical I/O adapter validates that one or more direct memory access addresses referenced by an incoming I/O transaction initiated through a memory mapped I/O operation are associated with a virtual adapter or virtual resource that is referenced by the incoming memory mapped I/O operation.

Abstract: A DMA controller controls DMA transfer in an information processing system. Input and output devices are a transfer source or a transfer destination in DMA transfer and request DMA transfer. A DMAC activating unit is provided with an event monitoring unit and an event register. The event register registers an event subject to monitoring. The event monitoring unit detects an event generated in the input and output devices and determines whether the detected event matches an event registered in the event register. If it is determined that the events match, the event monitoring unit activates the DMA controller.

Abstract: A data buffer that is a target for data received over a communication channel is examined, and a device associated with the communication channel is polled, to find, process, and return data transmitted over the channel. Other methods and apparatus to reduce network latency are described and claimed.

Abstract: Disclosed is a method and system for preparing a mirror batch within a data processing system. Upon determining that a first open batch is approaching or has reached a completion criteria, a controller may cause system elements contributing data to the first open batch to cease acknowledging transaction requests while not ceasing to execute the transaction requests.

Abstract: A processor arrangement having a strip structure for parallel data processing is configured so that local data from the individual processing units or strips is brought together in a rapid manner. Input data, intermediate data and/or output data from various processing units are linked together in an operation which is at least partially combinatory. The data linking operation is not clock controlled. The linking of the local data from various strips in this manner reduces delays in parallel data processing in the processor arrangement. The combinatory data linking operation can provide an overall data linking outcome within an individual clock cycle.

Abstract: An interface controller is connected to a host apparatus and a memory, and receiving multiple responses to one request. The interface controller includes a packet generation unit which adds header data to a request issued by the host apparatus to generate a request packet and outputs the request packet to the memory, a receive buffer which stores a response packet with respect to the request packet, a protocol generation unit which generates a response according to a prescribed protocol based on the response packet stored in the receive buffer, and outputs the response to the host apparatus, a maximum division number calculation unit which calculates a maximum division number of the request issued by the host apparatus, and a request issue control unit which gives a request issue permission to the host apparatus based on the maximum division number calculated by the maximum division number calculation unit, a maximum division number of processed request and a maximum division number of processed response.

Abstract: An electronic apparatus that transmits error information about setting of a block size to a host device includes an interface section that transmits and receives a command, a response and data to and from the host device. When the data is a predetermined length or more, the interface section executes multi-block transmission. Moreover, the electronic apparatus includes a data buffer, and a storage section that stores information about a block size. When the interface section receives a block size setting command transmitted from the host device and the block size is larger than a capacity of the data buffer, it transmits a response including error information about incapability of accepting the block size at the time which has a predetermined relation to the block size setting command.

Abstract: A method of transmitting data between storage virtualization controllers (SVCs) in a computer system is disclosed, in which there is an inter-controller communication channel (ICC) between the storage virtualization controllers. The method comprises the steps of: a central processing unit (CPU) of one storage virtualization controller (SVC) sending a data transfer request to an interface that establishes the ICC when the CPU needs to transmit information to the other SVC; and transmitting the information to the other SVC after the interface that establishes the ICC receives the data transfer request, and obtains the information.

Abstract: A new audio playback architecture may be used, which allows the use of much larger buffering than that used by a typical audio subsystem in a computing system to improve power efficiency of the system and at the same time allows to maintain the quality (e.g., fidelity and responsiveness) of the audio playback. The audio controller in the new architecture may be made to report back to the host system a more accurate indication of which audio frame is being set to the audio codec than a currently available audio controller does. Additionally, the controller is capable of re-fetching previously buffered (but not yet transmitted) data. Furthermore, buffers in both the audio controller and the main memory may be dynamically adjusted during playback of audio data and/or for different applications.

Abstract: A DMA circuit operates a plurality of DMA channels in parallel, enabling reduction of the circuit scale and fewer development processes. A channel manager circuit reads in sequence the control information for each DMA channel from control memory, performs analysis, and according to the divided DMA control sequence, performs state processing (DMA control). Further, the channel manager circuit updates the control information, writes back the control information to the control memory, and executes time-division control of the plurality of DMA channels. Hence the circuit scale can be reduced, contributing to decreased costs, and the number of development processes can be reduced.

Abstract: Methods and apparatus provide for assigning an identifier to a DMA command, the identifier for association with an entry of a DMA table containing status information regarding the DMA command; receiving an indication that a DMA data transfer defined by the DMA command has been completed; and updating the status information of the entry of the DMA table associated with the DMA data transfer to indicate that the DMA data transfer has been completed.