Abstract: A device comprising a chip, which is held in casting compound and on which a hollow structure is arranged is disclosed.

Abstract: In one exemplary embodiment, a method includes: providing a semiconductor device having a substrate, a nanowire, a first structure and a second structure, where the nanowire is suspended between the first structure and the second structure, where the first structure and the second structure overly the substrate; and performing atomic layer deposition to deposit a film on at least a portion of the semiconductor device, where performing atomic layer deposition to deposit the film includes performing atomic layer deposition to deposit the film on at least a surface of the nanowire.

Abstract: A method is provided for fabricating a CMOS device. The method includes providing a semiconductor substrate having a first active region and a second active region. The method also includes forming a first trench on the first active region using a first barrier layer and a second substitute gate electrode layer to protect a gate region on the second active region, followed by forming a first work function layer and a first metal gate in the first trench. Further, the method includes forming a second trench on the second active region using a second barrier layer to protect the first metal gate structure, followed by forming a second work function layer and a second metal gate in the second trench.

Abstract: Integrated circuits with electrostatic discharge (ESD) protection circuitry are provided. The ESD protection circuitry does not include polysilicon resistors. The ESD protection circuitry may include n-channel transistors coupled in parallel between an output node that is connected to an input/output pin and a ground terminal. The n-channel transistors may each have a drain terminal that is coupled to the output node through first metal paths and a source terminal that is coupled to the ground terminal through second metal paths. The first and second metal paths may be routed over gate terminals of the respective n-channel transistors to provide sufficient resistance. The first and second metal paths may provide desired pull-down resistance in the ESD protection circuitry so that the ESD protection circuitry can sink sufficient current through each of the n-channel transistors to protect internal circuitry from damage in an ESD event.

Abstract: A chalcogenide-based programmable conductor memory device and method of forming the device, wherein a nanoparticle is provided between an electrode and a chalcogenide glass region. The method of forming the nanoparticle utilizes a template over the electrode or random deposition of the nanoparticle.

Abstract: A method for fabricating a backside-illuminated sensor includes providing a thin film semiconductor lamina having a first conductivity, and forming a doped region having a second conductivity within the lamina and at a front surface of the lamina. The lamina may be provided as a free-standing lamina, or may be provided as a semiconductor donor body from which the lamina is cleaved. An electrical connection is formed to the doped region. A temporary carrier is contacted to the back surface of the semiconductor and later removed. A backside-illuminated sensor is fabricated from the semiconductor lamina, in which the thickness of the semiconductor lamina remains substantially unchanged during the fabrication process.

Abstract: An embodiment is directed to a method of manufacturing a polycrystalline silicon layer, the method including providing a crystallization substrate, the crystallization substrate having an amorphous silicon layer on a first substrate, providing a reflection substrate, the reflection substrate having a first region with a reflection panel therein and a second region without the reflection panel, disposing the crystallization substrate and the reflection substrate on one another, and selectively crystallizing the amorphous silicon layer by directing a laser beam onto the crystallization substrate and the reflection substrate, and reflecting the laser beam from the reflection panel.

Abstract: An embodiment of a process for manufacturing a power semiconductor device envisages the steps of: providing a body of semiconductor material having a top surface and having a first conductivity; forming columnar regions having a second type of conductivity within the body of semiconductor material, and surface extensions of the columnar regions above the top surface; and forming doped regions having the second type of conductivity, in the proximity of the top surface and in contact with the columnar regions. The doped regions are formed at least partially within the surface extensions of the columnar regions; the surface extensions and the doped regions have a non-planar surface pattern, in particular with a substantially V-shaped groove.

Abstract: An embedded transistor for an electrical device, such as a DRAM memory cell, and a method of manufacture thereof is provided. A trench is formed in a substrate and a gate dielectric and a gate electrode formed in the trench of the substrate. Source/drain regions are formed in the substrate on opposing sides of the trench. In an embodiment, one of the source/drain regions is coupled to a storage node and the other source/drain region is coupled to a bit line. In this embodiment, the gate electrode may be coupled to a word line to form a DRAM memory cell.

Abstract: The present invention relates to a light emitting diode with metal piles and one or more passivation layers and a method for making the diode including a first steps of performing mesa etching respectively on a first semiconductor layer and a second semiconductor layer belonging to stacked layers formed on a substrate in sequence! a second step of forming a reflector layer on the mesa-etched upper and side face! a third step of contacting one or more first electrodes with the first semiconductor layer and one or more second electrodes through the reflector layer with the second semiconductor layer; a fourth step of forming a first passivation layer on the reflector layer and the contacted electrodes; and a fifth step of connecting the first electrodes to a first bonding pad through one or more first electrode lines, bring one ends of vertical extensions having the shape of a metal pile into contact with one or more second electrodes, and connecting the other ends of the vertical extensions to a second bonding

Abstract: Provided are a light emitting device, a light emitting device package, and a lighting system. The light emitting device comprises a first semiconductor layer comprising a plurality of vacant space parts, an active layer on the first semiconductor layer, and a second conductive type semiconductor layer on the active layer. Each of the plurality of air-lenses has a thickness less than that of the first semiconductor layer.

Abstract: A structural alternative to retro doping to reduce transistor leakage is provided by providing a liner in a trench, undercutting a conduction channel region in an active semiconductor layer, etching a side, corner and/or bottom of the conduction channel where the undercut exposes semiconductor material in the active layer and replacing the removed portion of the conduction channel with insulator. This shaping of the conduction channel increases the distance to adjacent circuit elements which, if charged, could otherwise induce a voltage and cause a change in back-channel threshold in regions of the conduction channel and narrows and reduces cross-sectional area of the channel where the conduction in the channel is not well-controlled; both of which effects significantly reduce leakage of the transistor.

Abstract: The present invention discloses a wafer level image sensor packaging structure and a manufacturing method of the same. The manufacturing method includes the following steps: providing a silicon wafer, dicing the silicon wafer, providing a plurality of transparent lids, fabricating a plurality of semi-finished products, performing a packaging process, mounting solder balls, and cutting an encapsulant between the semi-finished products. The manufacturing method of the invention has the advantage of being straightforward, uncomplicated, and cost-saving. Thus, the wafer level image sensor package structure is lightweight, thin, and compact. To prevent the image sensor chip from cracking on impact during handling, the encapsulant will be arranged on the lateral sides of the semi-finished products during the packaging process.

Abstract: A micromachined microphone or speaker embedded within, or positioned on top of, a substrate suitable for carrying microelectronic chips and components. The acoustic element converts sound energy into electrical energy which is then amplified by electronic components positioned on the surface of the substrate. Alternatively, the acoustic element may be driven by electronics to produce sound. The substrate can be used in standard microelectronic packaging applications.

Abstract: A semiconductor switching device includes a package, and a semiconductor switching element provided in the package and having a collector electrode and an emitter electrode. A main collector terminal and a main emitter terminal reflect voltage drop generated during application of current by a floating component in the package. A second collector terminal and a second emitter terminal detect a voltage between the collector electrode and the emitter electrode without reflecting the voltage drop. A third emitter terminal is arranged close to the second emitter terminal, and detects the voltage drop generated between the main emitter terminal and the second emitter terminal.

Abstract: According to one embodiment, a light-emitting device includes a substrate, a plurality of pads and a plurality of light-emitting elements. The pads has electric conductance, and are arranged on the substrate. A reflecting layer which is formed by electroplating is provided on a surface of each of the pads. The light-emitting elements are mounted on the pads. A depressed part is left on the substrate. The depressed part is formed on the substrate by removing a pattern on the substrate, by which the pads are electrically connected.

Abstract: To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.

Abstract: To suppress short channel effects and obtain a high driving current by means of a semiconductor device having an MISFET wherein a material having high mobility and high dielectric constant, such as germanium, is used for a channel. A p-type well is formed on a surface of a p-type silicon substrate. A silicon germanium layer having a dielectric constant higher than that of the p-type silicon substrate is formed to have a thickness of 30 nm or less on the p-type well. Then, on the silicon germanium layer, a germanium layer having a dielectric constant higher than that of the silicon germanium layer is formed to have a thickness of 3-40 nm by epitaxial growing. The germanium layer is permitted to be a channel region; and a gate insulating film, a gate electrode, a side wall insulating film, an n-type impurity diffusion region and a silicide layer are formed.

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Abstract: Semiconductor structures are provided comprising a substrate and a epitaxial layer formed over the substrate, wherein the epitaxial layer comprises B; and one or more element selected from the group consisting of Zr, Hf and Al and has a thickness greater than 50 nm. Further, methods for integrating Group III nitrides onto a substrate comprising, forming an epitaxial buffer layer of a diboride of Zr, Hf, Al, or mixtures thereof, over a substrate; and forming a Group III nitride layer over the buffer layer, are provided which serve to thermally decouple the buffer layer from the underlying substrate, thereby greatly reducing the strain induced in the semiconductor structures upon fabrication and/or operation.